the same things, but the extent maps have to be managed differently,
since the two chipsets provide different memory and I/O region mapping
possibilities.
and PC-ish keyboard controller. (Actually, on alphas, the built-in PPI
(in the SIO) appears to be a lobotomized version of the original, but
i'd not call that a bad thing.) This driver should eventually handle all
speaker tone requests and keyboard commands, but for now it just maps
the relevant ports and passes them on to the keyboard and mouse drivers,
which are now its children (rather than children of ISA).
* Support for the new softint mechanism. Softints are now requested by
triggering an unused ICU hardware interrupt. The idea for this was
contributed by Phil Budne.
* Real probe code added.
* Duart info is now allocated only for devices that are present.
* Added IO-Recovery delays for 30mhz systems.
* Removed a few potential NULL-pointer references.
>One control block per target is insufficient if you have a full complement
>of targets attached and access those simultaneously (like in a ccd(4) array).
>We (now) allocate (somewhat arbitrarily) three per target.
>Noticed by Marshall Midden.
(1) after removing a shutdown hook (in shutdownhook_disestablish()),
free it. We created it, we have to free it. Without this,
shutdownhook_disestablish() leaks memory.
(2) in doshutdownhooks(), before running each hook, remove it from the
shutdown hook list. This makes sure that every hook is tried once
(because doshutdownhooks() is called from before rebooting, and
a fault in a shutdown hook will cause doshutdownhooks() to be called
again), but prevents the hooks from potentially being run infinitely
(as used to be possible, in the above-mentioned situation).
(e.g. from 0x3bc to 0x3bf, for example). Others may require more,
but until there's some special handling for them, 4 should be returned
so that on systems with I/O port accounting, the unit at 0x3bf can be
properly mapped, etc. (OK'd by mycroft.)
that their child busses can be attached after the PCI bus
autoconfiguration for their parent bus is done.
This works because:
(1) there can be at most one ISA/EISA bridge per PCI bus, and
(2) any ISA/EISA bridges must be attached to primary PCI
busses (i.e. bus zero).
That boils down to: there can only be one of these outstanding
at a time, it is cleared when configuring PCI bus 0 before any
subdevices have been found, and it is run after all subdevices
of PCI bus 0 have been found.
This (or something like it) is needed because there are some (legacy)
PCI devices which can show up as ISA/EISA devices as well (the prime
example of which are VGA controllers). If you attach ISA from a
PCI-ISA/EISA bridge, and the bridge is seen before the video board is,
the board can show up as an ISA device, and that can (bogusly)
complicate the PCI device's attach code, or make the PCI device not be
properly attached at all.
This could be done with machine-dependent code, but as more ports
add support for PCI (and PCI-ISA/EISA bridges) more will need it.
The i386 port could (perhaps should) be converted to use it as well.
devices actually do make sense on indirect-config busses, because you
might be able to have more than one of the busses! In addition, they're
useful because they don't require unit numbers to be wired down, so you
could e.g. have vga* at indirect? and vga* at direct?, and have the first
one found be unit number zero. Finally, devices which can divine their
own ports numbers, etc., actually should be cloning, even if you know you'll
only have one bus that they can live on.
don't machine check when a PCI Master Abort is signalled. This can
happen, for instance, when configuration space for a device that isn't
present is examined. When this is detected, act like we normally would
when machine checks are posted while examining nonexistant devices.
enabled (from the attach routine), and add comments as to why.
Some PALcode apparently 'saves' a clock interrupt for the kernel,
and if the clock interrupt handler is enabled at attach time, it
will be run when that interrupt hits, i.e. right after the spl0()
at the end of autoconfiguration. That would cause hardclock to be
run, but proc0's p_stats isn't set up by then, which would cause
hardclock to crash.
rather than and-ing 16G-1. That just strips the k0seg bits, rather
than making the false assumption that the physical address is going
to be in the lower 16G. That doesn't apply for CIA device-space
addresses, for instance.
even if PCI and the IDs are right), just for sanity, before declaring
success. Split the single 0x3b0 -> 0x3df allocation into three seperate
ones: 0x3b0 -> 0x3bc (leaving the 4 ports available for lpt),
0x3c0 -> 0x3cf, and 0x3d0 -> 0x3df. The former chunk has to be split
off if the lpt can exist there, and it's sort-of pretty to have each
group (based on second hex digit) have its own handle.
These alternative macros have a workaround for the STM^ bug in revision < 3
StrongARM CPU's that causes incorrect register saving if a cache line fill
is in progress during the STM.
cgd