Commit Graph

635 Commits

Author SHA1 Message Date
matt 7a12a9737c Revamp how SR(s) are loaded on the user/kernel boundary. We now load all
16 SR registers when transitioning between kernel and user.  Also, don't
reload the kernel SR(s) on every trap but only on traps from user space.
Instead of loading magic SRs for the kernel, load the kernel SRs from the
kernel_pmap_.  This makes trap_subr.S completely ignorant of SR uses and
so they can change with having to change trap_subr.S.  Also note that
since the user and kernel get complete SR sets, user VA space can now be
increased to 4GB if desired.
2002-06-26 01:14:45 +00:00
matt 7c77963b01 Set SR_PRKEY for user pmaps. For the kernel SR(s) set SR_SUKEY|SR_PRKEY.
Note that we never use a PTE PP of 0 or 1 (supervisor protection) so the
"key" is basically unused.  However, use SR_PRKEY for user space is
conceptionally the right thing to do.  Currently the kernel_pmap SR(s) are
ignored but that is going to be fixed shortly.
2002-06-26 01:10:20 +00:00
thorpej aaf6e7902d Add ENTRY_NOPROFILE(). 2002-06-23 17:26:58 +00:00
briggs 31d3b62eff Pick up support for a few more things for the IBM750FX: l2cache
configuration and temperature sensor support, for example.
2002-06-21 01:38:57 +00:00
matt 6fcbf3b943 Don't load the SR registers on a context switch. They get switched from
the user's SR registers to the kernel's SR registers on an exception or
interrupt from user level and restored with the user's SR register when the
exception or interrupt returns back to user level.
2002-06-21 00:46:18 +00:00
matt 365f1d6150 Add support for IBM750FX (used in latest iBooks). 2002-06-21 00:01:53 +00:00
matt da483421e8 Add IBM750FX (0x7000) 2002-06-20 23:51:22 +00:00
briggs 029a7e8e9a - The 8240 and 8245 have a 603 core -- add them to the 603 lists...
- Use atop(dcache_size / assoc) for uvm_page_recolor(ing) instead
  of  atop(dcache_line_size / assoc).
2002-06-19 17:43:30 +00:00
briggs d6cfd2cc8c Include the Processor ID for the MPC8245. 2002-06-19 17:39:26 +00:00
wrstuden 2eb3dc82d8 Fix recent bugs seen on Performa 4400 macppc's by
Makoto Fujiwara <makoto@ki.nu> and Manuel Bouyer <bouyer@netbsd.org>.
Help from Allen Briggs, Jason Thorpe, and Matt Thomas.

We need to call cpu_cache_probe() early in boot (machdep.c).
Add 603 info for completeness, and use NBPG not PAGESIZE, as the
latter relies on uvm being setup (cpu_subr.c).
Let uvm_page_recolor() be called before uvm has been set up; just
note the page coloring value (uvm_page.c).
2002-06-19 17:01:18 +00:00
matt c937154e18 Add a missing return; after print the 745x cache size(s). 2002-06-17 21:28:48 +00:00
christos 281c8c638b apply the fix from the powerpc port. this is almost a copy of powerpc/trap.c
and needs to be refactored.
2002-06-17 21:08:56 +00:00
christos eb5c1061a2 try to make this compile. 2002-06-17 21:07:40 +00:00
christos 3b50728cf4 MD systrace gluons. 2002-06-17 16:32:57 +00:00
kleink dd6cccb3f2 Add a case label for the 603ev cache (identical to 603e). 2002-06-11 22:24:35 +00:00
scw 9f2155138c Fix a botched pmap_vsid_bitmap[] index.
I'm surprised this worked as long as it did.
2002-06-05 15:55:51 +00:00
drochner d2b9876081 move initialization of the "struct pglist" returned by uvm_pglistalloc()
from the calling code into uvm_pglistalloc() itself for consistency
and easier error handling
2002-06-02 14:44:35 +00:00
lukem 06de426449 SIMPLEQ rototill:
- implement SIMPLEQ_REMOVE(head, elm, type, field).  whilst it's O(n),
  this mirrors the functionality of SLIST_REMOVE() (the other
  singly-linked list type) and FreeBSD's STAILQ_REMOVE()
- remove the unnecessary elm arg from SIMPLEQ_REMOVE_HEAD().
  this mirrors the functionality of SLIST_REMOVE_HEAD() (the other
  singly-linked list type) and FreeBSD's STAILQ_REMOVE_HEAD()
- remove notes about SIMPLEQ not supporting arbitrary element removal
- use SIMPLEQ_FOREACH() instead of home-grown for loops
- use SIMPLEQ_EMPTY() appropriately
- use SIMPLEQ_*() instead of accessing sqh_first,sqh_last,sqe_next directly
- reorder manual page; be consistent about how the types are listed
- other minor cleanups
2002-06-01 23:50:52 +00:00
tsubai 5fcd112b3a Add gcc 3.x version. 2002-06-01 09:22:44 +00:00
kleink 0bf753ef67 Cosmetics: there are exceptions to the PVR major/minor rule. 2002-05-31 20:10:45 +00:00
kleink 46b946bc5f Fill in real cache size/organization information and recolor; currently
doesn't make a difference except for the 604e.

XXX Does not consider L2 caches yet.
2002-05-31 15:04:14 +00:00
augustss e916f073c3 Add bus_space_vaddr(). 2002-05-31 11:31:30 +00:00
augustss cea3466ea6 Add NEED_BINARY, similar to NEED_SREC. 2002-05-19 18:57:33 +00:00
augustss 7202dc2f30 Add CPU_CI symbol so that bzero.S actually compiles on ports other than walnut. 2002-05-19 18:56:54 +00:00
jdolecek 2fc860bc0d make usable in LKM context (use #if defined(_KERNEL_OPT)) 2002-05-19 16:55:43 +00:00
augustss aaf6178285 Handle the "aligment" fault generated by DCBZ when the cache is off.
That way you can run the processor with caches off.
2002-05-19 06:35:45 +00:00
matt 0a6d35b7ed Nuke local extern label_t *db_recover; it's now in <ddb/db_extern.h> 2002-05-13 20:30:07 +00:00
matt f62dc5c664 Remove redundant declarations. 2002-05-13 07:04:24 +00:00
matt d210f0530b Eliminate commons. 2002-05-13 06:05:32 +00:00
kleink ba482b3950 * On the 601, obliterate all BAT entries when returning from kernel to
userlevel; this is necessary due to the 601, unlike other 6xx, having
  no concept of separated Valid_user vs. Valid_supervisor for BATs.
* When crossing the kernel/userlevel boundary, have platform-provided
  hooks set up the two fixed BAT entries, and possibly additional
  segment registers to redeem the 601's BAT limitations.

Both of the above are only built if the $MACHINE provides these hooks,
sparing others the pain.
2002-05-02 16:47:49 +00:00
kleink 3626919f4c Oops, swapped mtsrin operands in previous. 2002-04-23 17:14:45 +00:00
kleink 3a03930d13 Add a third argument to pmap_bootstrap() which platform-specific
initialization can use to specify additional segment registers to be set
up in the kernel pmap.
2002-04-23 12:41:04 +00:00
kleink 0b463cc8f9 Express tempsave and disisave addresses using the symbolic names of the
exception handlers which they are `borrowed' from.
2002-04-22 23:20:08 +00:00
kleink 0b82377f11 Fix a swapped register pasto(?) introduced in rev. 1.17. 2002-04-22 18:31:11 +00:00
kleink 884898e332 Convert the spill stack frame to use symbolic offset names; inspired by
a conversation with Matt Thomas.
2002-04-21 22:05:45 +00:00
kleink a641861ab8 Rig pmap_print_mmuregs() for the 601. 2002-04-19 20:56:56 +00:00
kleink 99d4b7c71f Unused; already implemented in libkern. 2002-04-18 21:42:36 +00:00
matt 66c475ca19 Use a common genassym.cf for all the PPC_MPC6XX ports. Add a makeoptions to
std.foo to indicate the directory to get genassym.cf from.  Add an intrframe
to <powerpc/frame.h> and make trap_subr.S use symbolic offsets into it.
2002-04-18 20:08:05 +00:00
kleink eb225418ed Don't do random replacement in isitrap601; just like isitrap. 2002-04-18 12:33:26 +00:00
matt 54d0dedd0c Cleanup the debug prints in pmap_enter. 2002-04-13 15:58:30 +00:00
briggs 4fb4a95b7e Install cpu.h. Noted in PR port-powerpc/16285 from smi@sm.sony.co.jp. 2002-04-10 15:36:42 +00:00
matt f8b9dbe468 Add some MPC745x L3CR cache definitions. 2002-04-03 00:12:41 +00:00
matt 830666e31e Clean the icache for pages when they are entered as executable and before
they were either not mapped at all or mapped as non-executable.  Round
memory regions in pmap_bootstrap.
2002-04-03 00:12:07 +00:00
matt 7e121bd39d Properly print out 745x cache information. 2002-04-03 00:09:52 +00:00
eeh 67c9b24c04 Follow the post-UBC semantics of resetting ref/mod collection inside of
pmap_clear_{reference,modify}().
2002-03-28 18:07:31 +00:00
kleink 1b6af7fb37 Add separate 601 versions of DSI/ISI trap entries, considering the
different battable entry format and the combined BAT implementation.
2002-03-27 15:40:46 +00:00
kleink 032762e1e9 On the 601, construct the CPU counter value from the RTC[UL] registers. 2002-03-26 21:50:39 +00:00
matt 12810ed37d Use size_t in prototype (so this will be LP64 clean for PPC64 someday).
Calculate len separately for icache & dcache in case each has different
cacheline widths.  Make the code for both loops the same except for the
dcbst/icbi.  Deal with sizes >=2GB properly (like that'll happen but ...)
2002-03-26 21:20:24 +00:00
kleink 7e9d845469 * Add MPC601 versions of BAT_VA_MATCH_P() and BAT_VALID_P().
* Make the extern declaration of the battable array incomplete;
  a given port might want to use a differently-sized definition to
  support the 601 BAT implementation, where blocks map up to 8M only.
2002-03-25 21:35:45 +00:00
briggs a2e0bd5a5d Use p->p_psstr instead of PS_STRINGS.
Tested on boot to multi-user on sandpoint.
2002-03-18 04:50:32 +00:00