add handling of a "close all" command
-split out code common with wsdisplay_delscreen() into
wsdisplay_closescreen()
-add ttymodem call to signal a HUP to the application if the screen
is closed
-add flag to force a "clear screen" on close (XXX should actually be
controlled from userland)
-remove checks for existence of "reset" entries in the emulations - this
is required now
- Fix an error in mips3_cpu_switch_resume(); ASID was not set correctly.
- Remove global variable 'curpcb' reference in mips1_proc_trampoline().
- Restore 'cpuregs.h'.
* Add the correct version of locore_mips1.S [ See previous revision for
description of changes ]
* Use defopt'ed MIPS3_L2CACHE_ABSENT in mips_machdep.c and pmap.c
to avoid generating extraneous code.
* GC pmap_set_referenced in pmap.c
reads. This avoids a problem where many writes will cause the driver
to allocate way too much memory.
This needs to change to a queueing system later, which will provide a
way to limit the memory consumed by the driver.
Without these changes, raidframe would use 24M or more on my machine when
the buffer cache dumped all its dirty blocks. Now it uses around 200k
or so.
minor of libc and the major of libutil). For little-endian architectures
merge the bnswap() assembly versions with nto* and hton* using symbols
aliasing. Use symbol renaming for the bswap function in this case to avoid
namespace pollution.
Declare bswap* in machine/bswap.h, not machine/endian.h. For little-endian
machines, common code for inline macros go in machine/byte_swap.h
Sync libkern with libc.
Adjust #include in kernel sources for machine/bswap.h.
Affected files:
include/mips_param.h, include/pcb.h,
mips/locore_mips1.S, mips/locore_mips3.S,
mips/mips_machdep.c, mips/vm_machdep.c
Issue:
So far, NetBSD/mips has not successfully got rid of fixed-address
kernel stack. USPACE (two 4KB pages) of each process has two distinct
KSEG2 addresses, both refer to a single physical storage; one address
for fixed range [ UADDR .. KERNELSTACK ), and another for "normal" KSEG2
address which was allocated by kernel memory manager and unique to each
others of processes.
"Doubly mapped" USPACE complicates context switch. Both address ranges
have to be managed with a special care of "wired" TLB entries which
are never replaced until next context switch to ensure no TLB miss for
USPACE access. It's equally crumbersome that MIPS processor's cache
machinary gets be confused about USPACE contents because there are two
distinct KSEG2 addresses to manipulate one physical storage.
Solution:
Purge KERNELSTACK constant for kernel stack pointer and replace
it with process unique values. Kernel stack bottom is located at
'curproc->p_addr + USPACE'. Context switch is simplified as it unloads
half of TLB hardwiring burden. It just manages the unique KSEG2 address
of each USPACE to be wired. As the side effect, switch_exit() has no
MIPS processor ISA dependent code anymore. It switchs kernel stack to
proc0's USPACE which has KSEG0 address and no need of TLB entry.
* Extensive use of 'genassym.cf'
To hide target port dependent and/or processor register size dependent
constants from assembler routines, 'genassym.cf' now has an extentive
set of definitions for various constants and offset values of
structural objects. This change will contribute possible NetBSD/mips64
portability too.
* Separation and rename of locore_r2000/_r4000.S
Those files are now indepedent standalones from locore.S to ease
maintainance works, and renamed to match MIPS processor ISA version.
* Changes in kernel mode exception handlers
Kernel mode exception handlers hold exception contexts by pushing a
certain set of register values on stack for resuming kernel mode
processing. This context is now represented with 'struct trapframe',
which is smaller than full scale (user mode) exception context 'struct
frame'. Stack consumption of kernel mode exception services is now
similar to 4.4BSD/mips.
* Relocation of exception frame
User mode context 'struct frame' is moved to the very bottom of kernel
stack at 'curproc->p_addr + USPACE - sizeof(struct frame)' This change
saves a bit of instructions on every return to user processes as it
eliminates reference to global variable 'curpcb' each time.
* Refurblished DDB backtrace routine
It's a growing concern to maintain stacktrace() code correctly. It
could be simplified by enforcing special arrangements for some of
obscure locore routines which violate usual coding conventions.
New backtrace code searchs for certain instructions peculiar to any of
function tails. Specifically, "jr ra" for normal function returns, "jr
k0" for MIPS1 exception handlers and "eret" for MIPS3 handlers.
* Support for 64-bit safe user code
Affected Files:
${ARCH}/include/pubassym.cf lib/libc/arch/mips/gen/*setjmp*
include/setjmp.h mips/include/[lots] mips/mips/[lots]
Solution:
We define macros REG_L/REG_S and SZREG for loading and storing
registers and for the size of registers. The exact meaning
of these is controlled by a macro (currently _MIPS64) which
allows one to treat the registers as either 32-bit or 64-bit.
There are data types mips_reg_t and mips_fpreg_t which represent
the true register sizes, and avoid confusing register_t.
We needed a way to dynamically gen the structure sizes of things
like sigcontext for setjmp.h, so we defined a pubassym.cf for
libc routines like setjmp and longjmp.
NetBSD/mips allows ${ARCH}'s to be defined which preserve
all 64-bits of registers across user context switches. There
are still a few niceties to clean up for kernel mode context
switches.
* Support for QED 52xx processors
Affected Files:
mips/locore_mips3.S mips/pmap.c include/locore.h
Issue:
The QED 52xx family of processors are targeted at low cost
embedded systems, (i.e. CPUs ~$30) for systems like routers, printers,
etc. We have added preliminary support for some of the idiosyncrasies
of this processor, e.g. no L2 cache, etc. More work needs to be
done here because with a modest 2-way L1 cache, some of the rampant
flushing has significant performance implications. However,
it doesn't crash, which is a start.
Solution:
A routine for flushing the cache based on virtual addresses was added;
a routine which deals with the two-way set associativity of the
5230 L1 cache was added, accomodations to 5230's instruction hazards
were added.
* TLB Miss code for mips3/mips4 processors cleaned up significantly.
Affected Files:
mips/locore_mips3.S mips/vm_machdep.c include/locore.h mips_machdep.c
Issue:
The TLB Miss handler exceeded the allowed size, which wasn't
a problem because there was no handler for when the processor
was in 64-bit mode. The handler for invalid TLB exceptions
also appears to have much vestigial code, which made it
difficult to understand.
Solution:
Use the XCONTEXT register to store a pointer to the segment
map table, this coupled with removing some dead code allows
the handlers to fit.
decoupled from long or int or long long. Define macros in asm.h to facilitate
choosing these on a port by port basis.
* Create <machine/pubassym.h> mechanism to allow jmp_buf structure size
to be calculated at system build time.
* Define _MIPS_BSD_SIM macro which specifies what calling style is appropritae
for the architecture. For 64-bit oriented systems set the Status Register
to allow 64-bit instructions.
* Remove UADDR related macros because kernel U structure is now mapped
normally.
* Separate cpu.h into cpu.h and cpuarch.h to keep things neat.
* Add support for QED 52xx processors
calls
-support use of 2 fonts simultanously; this costs the ability to
"highlight", ie to use the upper 8 colours
-define screen types "80x25bf" and "80x50bf" which use this ability
-add conditional code to deal with the weird mapping of pcvt's
supplemental fonts
to download fonts and a per-screen call to select a font
allows easier sharing of ressources in the display driver
change the parameters to the load_font driver vector to pass all
available font information
would appear that overloading the argument this way is used by SVR4 to `fall
off' the main context (uc_link being NULL) after a function set up using
makecontext() returns.
ipip_input(), and returns non-zero if mrt_ipip_input() handled the
packet.
XXX Eventually, the multicast code should probably use regular IP-IP
XXX `interfaces', but mrouted knows about the VIF table, etc.
up the interface to ip_mroute.c somewhat, and properly separates IP-IP
from GRE. (They are similar, but they are different protocols, and should
not be implemented in the same place.)
Because "linux_ipccall.h" cannot be included before "sys/shm.h" and
"sys/shm.h" needs to be included after "opt_sysv.h" include "opt_sysv.h"
in "linux_ipccall.c" again.
reported by Matthias Scheler <tron@lyssa.owl.de> in PR kern/6772.
- After receiving, check whether the receive DMA pointer became 0
what obviously happens if the list runs out of entries. Simply reinit
in this case. This fixes receive lockups after DDB use observed
by myself.
Unstall the receive engine if the ELINK_UPPKTSTATUS indicates that it
was stalled. (Don't know when this might happen. FreeBSD does so.)
+ Enable FIFO bursts, but also detect bogus 1040A with busted FIFO.
+ Use new MEMZERO crossplatform define.
+ Handle RQCS_QUEUE_FULL status case and let upper layer parse SCSI ststus
byte if nonzero (should be 0x28- Queue Full status)
+ Fold ISP_NVRAM_FIFO_THRESHOLD_128 into isp_fifo_threshold tag.
its real meaning
support allocation and deallocation of virtual screens at runtime
implement a "control device" (minor number = 255) and ioctl()s for screen
allocation/deallocation
minor fixes to consistency checks / error handling
get cache size from PROM info like the others
reset the cache type bits before setting our desired values
* smp cache flushing:
protect the cpu message bits with splhigh().
mappings for CADDR1 and CADDR2, unless we're built w/ -DDEBUG. Since
these addresses are only used in these routines, we can "lazily invalidate"
them by just using them again. This makes these routines a teeny bit faster,
as it saves 1 or 2 TBIS's per call.
Suggested by Leo Weppelman <leo@netbsd.org>.
pk