behind custom PCI<->GIO bridges:
- Set Engineering GIO Fast Ethernet (TI ThunderLAN)
- Phobos G100 (DEC 21140?)
- Phobos G130 (DEC 21143)
- Phobos G160 (DEC 21143)
All boards present the chipsets' pci configuration registers at some
defined offset in their slots' address space as well as device registers.
We simply allow the MI pci subsystem to attach the devices.
This has been tested with a G130 board (DEC 21143) and works well on IP20
and IP24. The Set Engineering board attaches, works fine when receiving and
lightly transmitting, but chokes for unknown reasons on heavy transmits.
The tl(4) driver may need some fixing.
gio bus arbiter parameters via imc(4) or pic(4).
Slots are identified by name: GIO_SLOT_GFX, GIO_SLOT_EXP1, GIO_SLOT_EXP2.
Provide some helper functions for establishing interrupts associated with
each slot and obtaining product descriptions.
configuration. These are to be used exclusively by a higher interface in
gio/gio.c.
Also add functions to enable, disable and query the state of SysAd bus
parity detection since certain gio(4) cards need to be able to disable
it in order to work around their own buggy implementations.
- Attempt to gracefully recover from a failed decrease_reservation or
increase_reservation, by avoiding physical memory loss.
- always store a machine address in ds_addr; this avoids some mistakes
where machine address would in some case be freed at physical address, or
mapped as physical address.
sharing of code with the AR5315, which has many similarities, but many
differences from the AR5312.
No functional change at this time, other than the cpu_model string
(and also sysctl.hw.model node) is changed to reflect the WiSoC cpu
name rather than the identification string in ROM (which tends to not
be very informative.)
Since kernels are always run out of KSEG0 (0xffffffff.8xxxxxxx), we can
take advantage of that if we load a 32 bit address (0x8xxxxxxx) that it
will be sign-extended to 64 bits (0xffffffff.8xxxxxxx).
So instead of 6 instructions (2 lui, 2 daddiu, dsll32, daddu) to load an
address, the normal number of 2 instructions (lui, daddiu) will be used.
Thus telling gcc/gas that symbols will always be 32 bits significantly
shrinks (by 10%) and speeds up a MIPS64 kernel.
matt