First pass at cleanup AR5312 WiSoC support to enable better & cleaner
sharing of code with the AR5315, which has many similarities, but many differences from the AR5312. No functional change at this time, other than the cpu_model string (and also sysctl.hw.model node) is changed to reflect the WiSoC cpu name rather than the identification string in ROM (which tends to not be very informative.)
This commit is contained in:
gdamore
parent
df7450f605
commit
5cdb703d36
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: autoconf.c,v 1.4 2006/06/05 05:14:37 gdamore Exp $ */
|
||||
/* $NetBSD: autoconf.c,v 1.5 2006/08/28 07:21:15 gdamore Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 2001 The NetBSD Foundation, Inc.
|
||||
@ -37,7 +37,7 @@
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__KERNEL_RCSID(0, "$NetBSD: autoconf.c,v 1.4 2006/06/05 05:14:37 gdamore Exp $");
|
||||
__KERNEL_RCSID(0, "$NetBSD: autoconf.c,v 1.5 2006/08/28 07:21:15 gdamore Exp $");
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
@ -49,7 +49,7 @@ __KERNEL_RCSID(0, "$NetBSD: autoconf.c,v 1.4 2006/06/05 05:14:37 gdamore Exp $")
|
||||
|
||||
#include <machine/bus.h>
|
||||
|
||||
#include <mips/atheros/include/ar531xreg.h>
|
||||
#include <mips/atheros/include/ar5312reg.h>
|
||||
#include <mips/atheros/include/ar531xvar.h>
|
||||
#include <mips/atheros/include/arbusvar.h>
|
||||
|
||||
@ -98,9 +98,9 @@ device_register(struct device *dev, void *aux)
|
||||
prop_data_t pd;
|
||||
const uint8_t *enet;
|
||||
|
||||
if (aa->aa_addr == AR531X_ENET0_BASE)
|
||||
if (aa->aa_addr == AR5312_ENET0_BASE)
|
||||
enet = info->enet0Mac;
|
||||
else if (aa->aa_addr == AR531X_ENET1_BASE)
|
||||
else if (aa->aa_addr == AR5312_ENET1_BASE)
|
||||
enet = info->enet1Mac;
|
||||
else
|
||||
return;
|
||||
@ -119,9 +119,9 @@ device_register(struct device *dev, void *aux)
|
||||
prop_data_t pd;
|
||||
const uint8_t *enet;
|
||||
|
||||
if (aa->aa_addr == AR531X_WLAN0_BASE)
|
||||
if (aa->aa_addr == AR5312_WLAN0_BASE)
|
||||
enet = info->wlan0Mac;
|
||||
else if (aa->aa_addr == AR531X_WLAN1_BASE)
|
||||
else if (aa->aa_addr == AR5312_WLAN1_BASE)
|
||||
enet = info->wlan1Mac;
|
||||
else
|
||||
return;
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: machdep.c,v 1.3 2006/06/05 05:14:37 gdamore Exp $ */
|
||||
/* $NetBSD: machdep.c,v 1.4 2006/08/28 07:21:15 gdamore Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2006 Urbana-Champaign Independent Media Center.
|
||||
@ -147,14 +147,11 @@
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
|
||||
__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.3 2006/06/05 05:14:37 gdamore Exp $");
|
||||
__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.4 2006/08/28 07:21:15 gdamore Exp $");
|
||||
|
||||
#include "opt_ddb.h"
|
||||
#include "opt_kgdb.h"
|
||||
|
||||
#include "opt_memsize.h"
|
||||
#include "opt_ethaddr.h"
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
#include <sys/kernel.h>
|
||||
@ -167,9 +164,6 @@ __KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.3 2006/06/05 05:14:37 gdamore Exp $");
|
||||
#include <sys/termios.h>
|
||||
#include <sys/ksyms.h>
|
||||
|
||||
#include <net/if.h>
|
||||
#include <net/if_ether.h>
|
||||
|
||||
#include <uvm/uvm_extern.h>
|
||||
|
||||
#include <dev/cons.h>
|
||||
@ -185,10 +179,8 @@ __KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.3 2006/06/05 05:14:37 gdamore Exp $");
|
||||
#include <mips/locore.h>
|
||||
#include <mips/cpuregs.h>
|
||||
|
||||
#include <mips/atheros/include/ar531xreg.h>
|
||||
#include <mips/atheros/include/ar531xvar.h>
|
||||
#include <mips/atheros/include/arbusvar.h>
|
||||
#include "com.h"
|
||||
|
||||
struct user *proc0paddr;
|
||||
|
||||
@ -208,12 +200,23 @@ phys_ram_seg_t mem_clusters[VM_PHYSSEG_MAX];
|
||||
|
||||
void mach_init(void); /* XXX */
|
||||
|
||||
void mdputc(char);
|
||||
void mdputs(const char *);
|
||||
void mdputx(int n);
|
||||
void mdputn(int n);
|
||||
static void
|
||||
cal_timer(void)
|
||||
{
|
||||
uint32_t cntfreq;
|
||||
|
||||
extern struct consdev com_arbus_consdev;
|
||||
cntfreq = curcpu()->ci_cpu_freq = ar531x_cpu_freq();
|
||||
|
||||
/* MIPS 4Kc CP0 counts every other clock */
|
||||
if (mips_cpu_flags & CPU_MIPS_DOUBLE_COUNT)
|
||||
cntfreq /= 2;
|
||||
|
||||
curcpu()->ci_cycles_per_hz = (cntfreq + hz / 2) / hz;
|
||||
|
||||
/* XXX: i don't understand this logic, it was borrowed from Malta */
|
||||
curcpu()->ci_divisor_delay = ((cntfreq + 500000) / 1000000);
|
||||
MIPS_SET_CI_RECIPRICAL(curcpu());
|
||||
}
|
||||
|
||||
void
|
||||
mach_init(void)
|
||||
@ -221,9 +224,7 @@ mach_init(void)
|
||||
caddr_t kernend;
|
||||
u_long first, last;
|
||||
caddr_t v;
|
||||
uint32_t memcfg, bank0, bank1;
|
||||
uint32_t memsize;
|
||||
const struct ar531x_boarddata *infop;
|
||||
|
||||
extern char edata[], end[]; /* XXX */
|
||||
|
||||
@ -232,12 +233,8 @@ mach_init(void)
|
||||
|
||||
memset(edata, 0, kernend - (caddr_t)edata);
|
||||
|
||||
infop = ar531x_board_info();
|
||||
if (infop == NULL)
|
||||
panic("No board info!");
|
||||
|
||||
/* set CPU model info for sysctl_hw */
|
||||
snprintf(cpu_model, 64, "%s", infop->boardName);
|
||||
snprintf(cpu_model, 64, "%s", ar531x_cpuname());
|
||||
|
||||
/*
|
||||
* Set up the exception vectors and CPU-specific function
|
||||
@ -253,7 +250,7 @@ mach_init(void)
|
||||
/*
|
||||
* Calibrate timers.
|
||||
*/
|
||||
ar531x_cal_timer();
|
||||
cal_timer();
|
||||
|
||||
/*
|
||||
* Set the VM page size.
|
||||
@ -275,26 +272,12 @@ mach_init(void)
|
||||
*/
|
||||
|
||||
/*
|
||||
* Determine the memory size. Use the `memsize' PMON
|
||||
* variable. If that's not available, panic.
|
||||
* Determine the memory size.
|
||||
*
|
||||
* Note: Reserve the first page! That's where the trap
|
||||
* vectors are located.
|
||||
*/
|
||||
memcfg = GETSDRAMREG(AR531X_SDRAMCTL_MEM_CFG1);
|
||||
bank0 = (memcfg & AR531X_MEM_CFG1_BANK0_MASK) >>
|
||||
AR531X_MEM_CFG1_BANK0_SHIFT;
|
||||
bank1 = (memcfg & AR531X_MEM_CFG1_BANK1_MASK) >>
|
||||
AR531X_MEM_CFG1_BANK1_SHIFT;
|
||||
|
||||
memsize = (bank0 ? (1 << (bank0 + 1)) : 0) +
|
||||
(bank1 ? (1 << (bank1 + 1)) : 0);
|
||||
memsize <<= 20;
|
||||
|
||||
/* allow compile time override */
|
||||
#if defined(MEMSIZE)
|
||||
memsize = MEMSIZE;
|
||||
#endif
|
||||
memsize = ar531x_memsize();
|
||||
|
||||
printf("Memory size: 0x%08x\n", memsize);
|
||||
physmem = btoc(memsize);
|
||||
@ -332,16 +315,15 @@ mach_init(void)
|
||||
curpcb->pcb_context[11] = MIPS_INT_MASK | MIPS_SR_INT_IE; /* SR */
|
||||
|
||||
/*
|
||||
* Clear previous AHB errors
|
||||
* Initialize busses.
|
||||
*/
|
||||
GETSYSREG(AR531X_SYSREG_AHBPERR);
|
||||
GETSYSREG(AR531X_SYSREG_AHBDMAE);
|
||||
ar531x_businit();
|
||||
|
||||
/*
|
||||
* Turn off (ignore) the hardware watchdog. If we got this
|
||||
* far, then we shouldn't need it anymore.
|
||||
*/
|
||||
PUTSYSREG(AR531X_SYSREG_WDOG_CTL, AR531X_WDOG_CTL_IGNORE);
|
||||
ar531x_wdog(0);
|
||||
|
||||
/*
|
||||
* Turn off watchpoint that may have been enabled by the
|
||||
@ -373,14 +355,7 @@ consinit(void)
|
||||
* Everything related to console initialization is done
|
||||
* in mach_init().
|
||||
*/
|
||||
#if NCOM > 0
|
||||
/* Setup polled serial for early console I/O */
|
||||
/* XXX: pass in CONSPEED? */
|
||||
com_arbus_cnattach(AR531X_UART0_BASE);
|
||||
#else
|
||||
panic("Not configured to use serial console!\n");
|
||||
/* not going to see that message now, are we? */
|
||||
#endif
|
||||
ar531x_consinit();
|
||||
}
|
||||
|
||||
void
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: wdog.c,v 1.1 2006/06/08 06:15:59 gdamore Exp $ */
|
||||
/* $NetBSD: wdog.c,v 1.2 2006/08/28 07:21:15 gdamore Exp $ */
|
||||
/*-
|
||||
* Copyright (c) 2006 Urbana-Champaign Independent Media Center.
|
||||
* Copyright (c) 2006 Garrett D'Amore.
|
||||
@ -79,7 +79,7 @@
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__KERNEL_RCSID(0, "$NetBSD: wdog.c,v 1.1 2006/06/08 06:15:59 gdamore Exp $");
|
||||
__KERNEL_RCSID(0, "$NetBSD: wdog.c,v 1.2 2006/08/28 07:21:15 gdamore Exp $");
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
@ -88,7 +88,6 @@ __KERNEL_RCSID(0, "$NetBSD: wdog.c,v 1.1 2006/06/08 06:15:59 gdamore Exp $");
|
||||
|
||||
#include <machine/cpu.h>
|
||||
|
||||
#include <mips/atheros/include/ar531xreg.h>
|
||||
#include <mips/atheros/include/ar531xvar.h>
|
||||
|
||||
#include <dev/sysmon/sysmonvar.h>
|
||||
@ -126,7 +125,7 @@ wdog_attach(struct device *parent, struct device *self, void *aux)
|
||||
{
|
||||
struct wdog_softc *sc = (void *)self;
|
||||
|
||||
sc->sc_mult = curcpu()->ci_cpu_freq / 4;
|
||||
sc->sc_mult = ar531x_sys_freq();
|
||||
sc->sc_wdog_period = WDOG_DEFAULT_PERIOD;
|
||||
sc->sc_wdog_max = 0xffffffffU / sc->sc_mult;
|
||||
sc->sc_wdog_reload = sc->sc_wdog_period * sc->sc_mult;
|
||||
@ -149,7 +148,7 @@ wdog_tickle(struct sysmon_wdog *smw)
|
||||
{
|
||||
struct wdog_softc *sc = smw->smw_cookie;
|
||||
|
||||
PUTSYSREG(AR531X_SYSREG_WDOG_TIMER, sc->sc_wdog_reload);
|
||||
ar531x_wdog(sc->sc_wdog_reload);
|
||||
return (0);
|
||||
}
|
||||
|
||||
@ -159,8 +158,7 @@ wdog_setmode(struct sysmon_wdog *smw)
|
||||
struct wdog_softc *sc = smw->smw_cookie;
|
||||
|
||||
if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) {
|
||||
PUTSYSREG(AR531X_SYSREG_WDOG_CTL, AR531X_WDOG_CTL_IGNORE);
|
||||
PUTSYSREG(AR531X_SYSREG_WDOG_TIMER, 0);
|
||||
ar531x_wdog(0);
|
||||
} else {
|
||||
|
||||
if (smw->smw_period == WDOG_PERIOD_DEFAULT)
|
||||
@ -177,8 +175,7 @@ wdog_setmode(struct sysmon_wdog *smw)
|
||||
sc->sc_wdog_reload = sc->sc_wdog_period * sc->sc_mult;
|
||||
}
|
||||
|
||||
PUTSYSREG(AR531X_SYSREG_WDOG_TIMER, sc->sc_wdog_reload);
|
||||
PUTSYSREG(AR531X_SYSREG_WDOG_CTL, AR531X_WDOG_CTL_RESET);
|
||||
ar531x_wdog(sc->sc_wdog_reload);
|
||||
}
|
||||
|
||||
return (0);
|
||||
|
||||
@ -1,11 +1,12 @@
|
||||
/* $Id: ar531x_timer.c,v 1.1 2006/03/21 08:15:19 gdamore Exp $ */
|
||||
/* $NetBSD: ar5312.c,v 1.1 2006/08/28 07:21:15 gdamore Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2006 Urbana-Champaign Independent Media Center.
|
||||
* Copyright (c) 2006 Garrett D'Amore.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This code was written by Garrett D'Amore for the Champaign-Urbana
|
||||
* Community Wireless Network Project.
|
||||
* Portions of this code were written by Garrett D'Amore for the
|
||||
* Champaign-Urbana Community Wireless Network Project.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or
|
||||
* without modification, are permitted provided that the following
|
||||
@ -40,22 +41,124 @@
|
||||
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__KERNEL_RCSID(0, "$NetBSD: ar531x_timer.c,v 1.1 2006/03/21 08:15:19 gdamore Exp $");
|
||||
/*
|
||||
* This file includes a bunch of implementation specific bits for
|
||||
* AR5312, which differents these from other members of the AR5315
|
||||
* family.
|
||||
*/
|
||||
#include "opt_ddb.h"
|
||||
#include "opt_kgdb.h"
|
||||
|
||||
#include "opt_memsize.h"
|
||||
#include <sys/param.h>
|
||||
#include <sys/kernel.h>
|
||||
#include <sys/systm.h>
|
||||
#include <sys/kernel.h>
|
||||
#include <sys/buf.h>
|
||||
|
||||
#include <mips/cache.h>
|
||||
#include <mips/locore.h>
|
||||
#include <mips/cpuregs.h>
|
||||
|
||||
#include <mips/atheros/include/ar531xreg.h>
|
||||
#include <mips/atheros/include/ar5312reg.h>
|
||||
#include <mips/atheros/include/ar531xvar.h>
|
||||
#include <mips/atheros/include/arbusvar.h>
|
||||
#include "com.h"
|
||||
|
||||
uint32_t
|
||||
ar531x_memsize(void)
|
||||
{
|
||||
uint32_t memsize;
|
||||
uint32_t memcfg, bank0, bank1;
|
||||
|
||||
/*
|
||||
* Determine the memory size. Use the `memsize' PMON
|
||||
* variable. If that's not available, panic.
|
||||
*
|
||||
* NB: we allow compile time override
|
||||
*/
|
||||
#if defined(MEMSIZE)
|
||||
memsize = MEMSIZE;
|
||||
#else
|
||||
memcfg = GETSDRAMREG(AR5312_SDRAMCTL_MEM_CFG1);
|
||||
bank0 = (memcfg & AR5312_MEM_CFG1_BANK0_MASK) >>
|
||||
AR5312_MEM_CFG1_BANK0_SHIFT;
|
||||
bank1 = (memcfg & AR5312_MEM_CFG1_BANK1_MASK) >>
|
||||
AR5312_MEM_CFG1_BANK1_SHIFT;
|
||||
|
||||
memsize = (bank0 ? (1 << (bank0 + 1)) : 0) +
|
||||
(bank1 ? (1 << (bank1 + 1)) : 0);
|
||||
memsize <<= 20;
|
||||
#endif
|
||||
|
||||
return (memsize);
|
||||
}
|
||||
|
||||
void
|
||||
ar531x_cal_timer(void)
|
||||
ar531x_wdog(uint32_t period)
|
||||
{
|
||||
uint32_t wisoc = GETSYSREG(AR531X_SYSREG_REVISION);
|
||||
|
||||
if (period == 0) {
|
||||
PUTSYSREG(AR5312_SYSREG_WDOG_CTL, AR5312_WDOG_CTL_IGNORE);
|
||||
PUTSYSREG(AR5312_SYSREG_WDOG_TIMER, 0);
|
||||
} else {
|
||||
PUTSYSREG(AR5312_SYSREG_WDOG_TIMER, period);
|
||||
PUTSYSREG(AR5312_SYSREG_WDOG_CTL, AR5312_WDOG_CTL_RESET);
|
||||
}
|
||||
}
|
||||
|
||||
const char *
|
||||
ar531x_cpuname(void)
|
||||
{
|
||||
uint32_t revision;
|
||||
|
||||
revision = GETSYSREG(AR5312_SYSREG_REVISION);
|
||||
switch (AR5312_REVISION_MAJOR(revision)) {
|
||||
case AR5312_REVISION_MAJ_AR5311:
|
||||
return ("Atheros AR5311");
|
||||
case AR5312_REVISION_MAJ_AR5312:
|
||||
return ("Atheros AR5312");
|
||||
case AR5312_REVISION_MAJ_AR2313:
|
||||
return ("Atheros AR2313");
|
||||
case AR5312_REVISION_MAJ_AR5315:
|
||||
return ("Atheros AR5315");
|
||||
default:
|
||||
return ("Atheros AR531X");
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
ar531x_consinit(void)
|
||||
{
|
||||
/*
|
||||
* Everything related to console initialization is done
|
||||
* in mach_init().
|
||||
*/
|
||||
#if NCOM > 0
|
||||
/* Setup polled serial for early console I/O */
|
||||
/* XXX: pass in CONSPEED? */
|
||||
com_arbus_cnattach(AR5312_UART0_BASE);
|
||||
#else
|
||||
panic("Not configured to use serial console!\n");
|
||||
/* not going to see that message now, are we? */
|
||||
#endif
|
||||
}
|
||||
|
||||
void
|
||||
ar531x_businit(void)
|
||||
|
||||
{
|
||||
/*
|
||||
* Clear previous AHB errors
|
||||
*/
|
||||
GETSYSREG(AR5312_SYSREG_AHBPERR);
|
||||
GETSYSREG(AR5312_SYSREG_AHBDMAE);
|
||||
}
|
||||
|
||||
uint32_t
|
||||
ar531x_cpu_freq(void)
|
||||
{
|
||||
static uint32_t cpufreq;
|
||||
uint32_t wisoc = GETSYSREG(AR5312_SYSREG_REVISION);
|
||||
|
||||
uint32_t predivmask;
|
||||
uint32_t predivshift;
|
||||
@ -64,7 +167,6 @@ ar531x_cal_timer(void)
|
||||
uint32_t doublermask;
|
||||
uint32_t divisor;
|
||||
uint32_t multiplier;
|
||||
uint32_t cpufreq;
|
||||
uint32_t clockctl;
|
||||
|
||||
const int predivide_table[4] = { 1, 2, 4, 5 };
|
||||
@ -78,7 +180,11 @@ ar531x_cal_timer(void)
|
||||
* be very accurate -- WiFi requires usec resolution timers.
|
||||
*/
|
||||
|
||||
if (AR531X_REVISION_MAJOR(wisoc) == AR531X_REVISION_MAJ_AR2313) {
|
||||
if (cpufreq) {
|
||||
return cpufreq;
|
||||
}
|
||||
|
||||
if (AR5312_REVISION_MAJOR(wisoc) == AR5312_REVISION_MAJ_AR2313) {
|
||||
predivmask = AR2313_CLOCKCTL_PREDIVIDE_MASK;
|
||||
predivshift = AR2313_CLOCKCTL_PREDIVIDE_SHIFT;
|
||||
multmask = AR2313_CLOCKCTL_MULTIPLIER_MASK;
|
||||
@ -92,7 +198,11 @@ ar531x_cal_timer(void)
|
||||
doublermask = AR5312_CLOCKCTL_DOUBLER_MASK;
|
||||
}
|
||||
|
||||
clockctl = GETSYSREG(AR531X_SYSREG_CLOCKCTL);
|
||||
/*
|
||||
* Note that the source clock involved here is a 40MHz.
|
||||
*/
|
||||
|
||||
clockctl = GETSYSREG(AR5312_SYSREG_CLOCKCTL);
|
||||
divisor = predivide_table[(clockctl & predivmask) >> predivshift];
|
||||
multiplier = (clockctl & multmask) >> multshift;
|
||||
|
||||
@ -101,21 +211,11 @@ ar531x_cal_timer(void)
|
||||
|
||||
cpufreq = (40000000 / divisor) * multiplier;
|
||||
|
||||
/* MIPS 4Kc CP0 counts every other clock */
|
||||
if (mips_cpu_flags & CPU_MIPS_DOUBLE_COUNT)
|
||||
cpufreq /= 2;
|
||||
|
||||
curcpu()->ci_cycles_per_hz = (cpufreq + hz / 2) / hz;
|
||||
|
||||
/* XXX: i don't understand this logic, it was borrowed from Malta */
|
||||
curcpu()->ci_divisor_delay = ((cpufreq + 500000) / 1000000);
|
||||
MIPS_SET_CI_RECIPRICAL(curcpu());
|
||||
|
||||
/*
|
||||
* Get correct cpu frequency if the CPU runs at twice the
|
||||
* external/cp0-count frequency.
|
||||
*/
|
||||
curcpu()->ci_cpu_freq = cpufreq;
|
||||
if (mips_cpu_flags & CPU_MIPS_DOUBLE_COUNT)
|
||||
curcpu()->ci_cpu_freq *= 2;
|
||||
return (cpufreq);
|
||||
}
|
||||
|
||||
uint32_t
|
||||
ar531x_sys_freq(void)
|
||||
{
|
||||
return (ar531x_cpu_freq() / 4);
|
||||
}
|
||||
@ -1,4 +1,4 @@
|
||||
/* $Id: ar531x_intr.c,v 1.2 2006/03/28 03:43:58 gdamore Exp $ */
|
||||
/* $Id: ar5312_intr.c,v 1.1 2006/08/28 07:21:15 gdamore Exp $ */
|
||||
/*
|
||||
* Copyright (c) 2006 Urbana-Champaign Independent Media Center.
|
||||
* Copyright (c) 2006 Garrett D'Amore.
|
||||
@ -41,7 +41,7 @@
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__KERNEL_RCSID(0, "$NetBSD: ar531x_intr.c,v 1.2 2006/03/28 03:43:58 gdamore Exp $");
|
||||
__KERNEL_RCSID(0, "$NetBSD: ar5312_intr.c,v 1.1 2006/08/28 07:21:15 gdamore Exp $");
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/queue.h>
|
||||
@ -54,7 +54,7 @@ __KERNEL_RCSID(0, "$NetBSD: ar531x_intr.c,v 1.2 2006/03/28 03:43:58 gdamore Exp
|
||||
#include <machine/intr.h>
|
||||
|
||||
#include <mips/locore.h>
|
||||
#include <mips/atheros/include/ar531xreg.h>
|
||||
#include <mips/atheros/include/ar5312reg.h>
|
||||
#include <mips/atheros/include/ar531xvar.h>
|
||||
|
||||
/*
|
||||
@ -72,8 +72,8 @@ __KERNEL_RCSID(0, "$NetBSD: ar531x_intr.c,v 1.2 2006/03/28 03:43:58 gdamore Exp
|
||||
*/
|
||||
|
||||
#define REGVAL(x) *((volatile uint32_t *)(MIPS_PHYS_TO_KSEG1((x))))
|
||||
#define GETREG(x) REGVAL((x) + AR531X_SYSREG_BASE)
|
||||
#define PUTREG(x,v) (REGVAL((x) + AR531X_SYSREG_BASE)) = (v)
|
||||
#define GETREG(x) REGVAL((x) + AR5312_SYSREG_BASE)
|
||||
#define PUTREG(x,v) (REGVAL((x) + AR5312_SYSREG_BASE)) = (v)
|
||||
|
||||
#define NINTRS 5 /* MIPS INT0-INT6 (7 is clock interrupt) */
|
||||
#define NIRQS 7 /* bits in Miscellaneous Interrupt Status Register */
|
||||
@ -133,7 +133,7 @@ const uint32_t mips_ipl_si_to_sr[_IPL_NSOFT] = {
|
||||
MIPS_SOFT_INT_MASK_0, /* IPL_SOFTSERIAL */
|
||||
};
|
||||
|
||||
static const char *ar531x_cpuintrnames[NINTRS] = {
|
||||
static const char *ar5312_cpuintrnames[NINTRS] = {
|
||||
"int 2 (wlan0)",
|
||||
"int 3 (enet0)",
|
||||
"int 4 (enet1)",
|
||||
@ -141,7 +141,7 @@ static const char *ar531x_cpuintrnames[NINTRS] = {
|
||||
"int 6 (misc)",
|
||||
};
|
||||
|
||||
static const char *ar531x_miscintrnames[NIRQS] = {
|
||||
static const char *ar5312_miscintrnames[NIRQS] = {
|
||||
"misc 0 (timer)",
|
||||
"misc 1 (AHBproc error)",
|
||||
"misc 2 (AHBdma error)",
|
||||
@ -151,8 +151,8 @@ static const char *ar531x_miscintrnames[NIRQS] = {
|
||||
"misc 6 (watchdog)"
|
||||
};
|
||||
|
||||
static struct ar531x_intr ar531x_cpuintrs[NINTRS];
|
||||
static struct ar531x_intr ar531x_miscintrs[NIRQS];
|
||||
static struct ar531x_intr ar5312_cpuintrs[NINTRS];
|
||||
static struct ar531x_intr ar5312_miscintrs[NIRQS];
|
||||
|
||||
static int ar531x_miscintr(void *);
|
||||
|
||||
@ -162,20 +162,20 @@ ar531x_intr_init(void)
|
||||
int i;
|
||||
|
||||
for (i = 0; i < NINTRS; i++) {
|
||||
LIST_INIT(&ar531x_cpuintrs[i].intr_l);
|
||||
evcnt_attach_dynamic(&ar531x_cpuintrs[i].intr_count,
|
||||
EVCNT_TYPE_INTR, NULL, "mips", ar531x_cpuintrnames[i]);
|
||||
LIST_INIT(&ar5312_cpuintrs[i].intr_l);
|
||||
evcnt_attach_dynamic(&ar5312_cpuintrs[i].intr_count,
|
||||
EVCNT_TYPE_INTR, NULL, "mips", ar5312_cpuintrnames[i]);
|
||||
}
|
||||
|
||||
for (i = 0; i < NIRQS; i++) {
|
||||
LIST_INIT(&ar531x_miscintrs[i].intr_l);
|
||||
evcnt_attach_dynamic(&ar531x_miscintrs[i].intr_count,
|
||||
EVCNT_TYPE_INTR, NULL, "ar531x", ar531x_miscintrnames[i]);
|
||||
LIST_INIT(&ar5312_miscintrs[i].intr_l);
|
||||
evcnt_attach_dynamic(&ar5312_miscintrs[i].intr_count,
|
||||
EVCNT_TYPE_INTR, NULL, "ar5312", ar5312_miscintrnames[i]);
|
||||
}
|
||||
|
||||
/* make sure we start without any misc interrupts enabled */
|
||||
GETREG(AR531X_SYSREG_MISC_INTSTAT);
|
||||
PUTREG(AR531X_SYSREG_MISC_INTMASK, 0);
|
||||
GETREG(AR5312_SYSREG_MISC_INTSTAT);
|
||||
PUTREG(AR5312_SYSREG_MISC_INTMASK, 0);
|
||||
|
||||
/* make sure we register the MISC interrupt handler */
|
||||
ar531x_intr_establish(NINTRS - 1, ar531x_miscintr, NULL);
|
||||
@ -200,7 +200,7 @@ ar531x_intr_establish(int intr, int (*func)(void *), void *arg)
|
||||
|
||||
s = splhigh();
|
||||
|
||||
LIST_INSERT_HEAD(&ar531x_cpuintrs[intr].intr_l, ih, ih_q);
|
||||
LIST_INSERT_HEAD(&ar5312_cpuintrs[intr].intr_l, ih, ih_q);
|
||||
|
||||
/*
|
||||
* The MIPS CPU interrupts are enabled at boot time, so they
|
||||
@ -244,16 +244,16 @@ ar531x_misc_intr_establish(int irq, int (*func)(void *), void *arg)
|
||||
|
||||
s = splhigh();
|
||||
|
||||
first = LIST_EMPTY(&ar531x_miscintrs[irq].intr_l);
|
||||
first = LIST_EMPTY(&ar5312_miscintrs[irq].intr_l);
|
||||
|
||||
LIST_INSERT_HEAD(&ar531x_miscintrs[irq].intr_l, ih, ih_q);
|
||||
LIST_INSERT_HEAD(&ar5312_miscintrs[irq].intr_l, ih, ih_q);
|
||||
|
||||
if (first) {
|
||||
uint32_t mask;
|
||||
mask = GETREG(AR531X_SYSREG_MISC_INTMASK);
|
||||
mask = GETREG(AR5312_SYSREG_MISC_INTMASK);
|
||||
mask |= (1 << irq);
|
||||
PUTREG(AR531X_SYSREG_MISC_INTMASK, mask);
|
||||
GETREG(AR531X_SYSREG_MISC_INTMASK); /* flush wbuffer */
|
||||
PUTREG(AR5312_SYSREG_MISC_INTMASK, mask);
|
||||
GETREG(AR5312_SYSREG_MISC_INTMASK); /* flush wbuffer */
|
||||
}
|
||||
|
||||
splx(s);
|
||||
@ -270,12 +270,12 @@ ar531x_misc_intr_disestablish(void *arg)
|
||||
s = splhigh();
|
||||
|
||||
LIST_REMOVE(ih, ih_q);
|
||||
if (LIST_EMPTY(&ar531x_miscintrs[ih->ih_irq].intr_l)) {
|
||||
if (LIST_EMPTY(&ar5312_miscintrs[ih->ih_irq].intr_l)) {
|
||||
uint32_t mask;
|
||||
mask = GETREG(AR531X_SYSREG_MISC_INTMASK);
|
||||
mask = GETREG(AR5312_SYSREG_MISC_INTMASK);
|
||||
mask &= ~(1 << ih->ih_irq);
|
||||
PUTREG(AR531X_SYSREG_MISC_INTMASK, mask);
|
||||
GETREG(AR531X_SYSREG_MISC_INTMASK); /* flush wbuffer */
|
||||
PUTREG(AR5312_SYSREG_MISC_INTMASK, mask);
|
||||
GETREG(AR5312_SYSREG_MISC_INTMASK); /* flush wbuffer */
|
||||
}
|
||||
|
||||
splx(s);
|
||||
@ -292,14 +292,14 @@ ar531x_miscintr(void *arg)
|
||||
int rv = 0;
|
||||
struct ar531x_intrhand *ih;
|
||||
|
||||
isr = GETREG(AR531X_SYSREG_MISC_INTSTAT);
|
||||
mask = GETREG(AR531X_SYSREG_MISC_INTMASK);
|
||||
isr = GETREG(AR5312_SYSREG_MISC_INTSTAT);
|
||||
mask = GETREG(AR5312_SYSREG_MISC_INTMASK);
|
||||
|
||||
for (index = 0; index < NIRQS; index++) {
|
||||
|
||||
if (isr & mask & (1 << index)) {
|
||||
ar531x_miscintrs[index].intr_count.ev_count++;
|
||||
LIST_FOREACH(ih, &ar531x_miscintrs[index].intr_l, ih_q)
|
||||
ar5312_miscintrs[index].intr_count.ev_count++;
|
||||
LIST_FOREACH(ih, &ar5312_miscintrs[index].intr_l, ih_q)
|
||||
rv |= (*ih->ih_func)(ih->ih_arg);
|
||||
}
|
||||
}
|
||||
@ -319,8 +319,8 @@ ar531x_cpuintr(uint32_t status, uint32_t cause, uint32_t pc, uint32_t ipending)
|
||||
mask = MIPS_INT_MASK_0 << index;
|
||||
|
||||
if (ipending & mask) {
|
||||
ar531x_cpuintrs[index].intr_count.ev_count++;
|
||||
LIST_FOREACH(ih, &ar531x_cpuintrs[index].intr_l, ih_q)
|
||||
ar5312_cpuintrs[index].intr_count.ev_count++;
|
||||
LIST_FOREACH(ih, &ar5312_cpuintrs[index].intr_l, ih_q)
|
||||
(*ih->ih_func)(ih->ih_arg);
|
||||
cause &= ~mask;
|
||||
}
|
||||
@ -1,4 +1,4 @@
|
||||
/* $Id: ar531x_board.c,v 1.3 2006/06/05 05:14:38 gdamore Exp $ */
|
||||
/* $Id: ar531x_board.c,v 1.4 2006/08/28 07:21:15 gdamore Exp $ */
|
||||
/*
|
||||
* Copyright (c) 2006 Urbana-Champaign Independent Media Center.
|
||||
* Copyright (c) 2006 Garrett D'Amore.
|
||||
@ -40,14 +40,14 @@
|
||||
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
#include <sys/cdefs.h>
|
||||
__KERNEL_RCSID(0, "$NetBSD: ar531x_board.c,v 1.3 2006/06/05 05:14:38 gdamore Exp $");
|
||||
__KERNEL_RCSID(0, "$NetBSD: ar531x_board.c,v 1.4 2006/08/28 07:21:15 gdamore Exp $");
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
#include <sys/device.h>
|
||||
|
||||
#include <machine/bus.h>
|
||||
#include <mips/atheros/include/ar531xreg.h>
|
||||
#include <mips/atheros/include/ar5312reg.h>
|
||||
#include <mips/atheros/include/ar531xvar.h>
|
||||
|
||||
#include <contrib/dev/ath/ah_soc.h>
|
||||
@ -67,31 +67,31 @@ ar531x_board_info(void)
|
||||
|
||||
if (board == NULL) {
|
||||
/* configure flash bank 0 */
|
||||
fctl = REGVAL(AR531X_FLASHCTL_BASE + AR531X_FLASHCTL_0) &
|
||||
AR531X_FLASHCTL_MW_MASK;
|
||||
fctl = REGVAL(AR5312_FLASHCTL_BASE + AR5312_FLASHCTL_0) &
|
||||
AR5312_FLASHCTL_MW_MASK;
|
||||
|
||||
fctl |=
|
||||
AR531X_FLASHCTL_E |
|
||||
AR531X_FLASHCTL_RBLE |
|
||||
AR531X_FLASHCTL_AC_8M |
|
||||
(1 << AR531X_FLASHCTL_IDCY_SHIFT) |
|
||||
(7 << AR531X_FLASHCTL_WST1_SHIFT) |
|
||||
(7 << AR531X_FLASHCTL_WST2_SHIFT);
|
||||
AR5312_FLASHCTL_E |
|
||||
AR5312_FLASHCTL_RBLE |
|
||||
AR5312_FLASHCTL_AC_8M |
|
||||
(1 << AR5312_FLASHCTL_IDCY_SHIFT) |
|
||||
(7 << AR5312_FLASHCTL_WST1_SHIFT) |
|
||||
(7 << AR5312_FLASHCTL_WST2_SHIFT);
|
||||
|
||||
REGVAL(AR531X_FLASHCTL_BASE + AR531X_FLASHCTL_0) = fctl;
|
||||
REGVAL(AR5312_FLASHCTL_BASE + AR5312_FLASHCTL_0) = fctl;
|
||||
|
||||
REGVAL(AR531X_FLASHCTL_BASE + AR531X_FLASHCTL_1) &=
|
||||
~(AR531X_FLASHCTL_E | AR531X_FLASHCTL_AC_MASK);
|
||||
REGVAL(AR5312_FLASHCTL_BASE + AR5312_FLASHCTL_1) &=
|
||||
~(AR5312_FLASHCTL_E | AR5312_FLASHCTL_AC_MASK);
|
||||
|
||||
REGVAL(AR531X_FLASHCTL_BASE + AR531X_FLASHCTL_2) &=
|
||||
~(AR531X_FLASHCTL_E | AR531X_FLASHCTL_AC_MASK);
|
||||
REGVAL(AR5312_FLASHCTL_BASE + AR5312_FLASHCTL_2) &=
|
||||
~(AR5312_FLASHCTL_E | AR5312_FLASHCTL_AC_MASK);
|
||||
|
||||
/* search backward in the flash looking for the signature */
|
||||
ptr = (const uint8_t *) MIPS_PHYS_TO_KSEG1(AR531X_FLASH_END - 0x1000);
|
||||
ptr = (const uint8_t *) MIPS_PHYS_TO_KSEG1(AR5312_FLASH_END - 0x1000);
|
||||
end = ptr - (500 * 1024); /* NB: max 500KB window */
|
||||
/* XXX validate end */
|
||||
for (; ptr > end; ptr -= 0x1000)
|
||||
if (*(const uint32_t *)ptr == AR531X_BOARD_MAGIC) {
|
||||
if (*(const uint32_t *)ptr == AR531X_BD_MAGIC) {
|
||||
board = (const struct ar531x_boarddata *) ptr;
|
||||
break;
|
||||
}
|
||||
@ -117,7 +117,7 @@ ar531x_radio_info(void)
|
||||
baddr = (const uint8_t *) board;
|
||||
ptr = baddr + 0x1000;
|
||||
end = (const uint8_t *)
|
||||
MIPS_PHYS_TO_KSEG1(AR531X_FLASH_END-0x1000);
|
||||
MIPS_PHYS_TO_KSEG1(AR5312_FLASH_END-0x1000);
|
||||
again:
|
||||
for (; ptr < end; ptr += 0x1000)
|
||||
if (*(const uint32_t *)ptr != 0xffffffff) {
|
||||
@ -125,11 +125,11 @@ ar531x_radio_info(void)
|
||||
goto done;
|
||||
}
|
||||
/* sort of an Algol-style for loop ... */
|
||||
if (end == (uint8_t *) MIPS_PHYS_TO_KSEG1(AR531X_FLASH_END)) {
|
||||
if (end == (uint8_t *) MIPS_PHYS_TO_KSEG1(AR5312_FLASH_END)) {
|
||||
/* NB: AR2316 has radio data in a different location */
|
||||
ptr = baddr + 0xf8;
|
||||
end = (const uint8_t *)
|
||||
MIPS_PHYS_TO_KSEG1(AR531X_FLASH_END-0x1000 + 0xf8);
|
||||
MIPS_PHYS_TO_KSEG1(AR5312_FLASH_END-0x1000 + 0xf8);
|
||||
goto again;
|
||||
}
|
||||
}
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $Id: arbus.c,v 1.8 2006/07/13 21:38:24 gdamore Exp $ */
|
||||
/* $Id: arbus.c,v 1.9 2006/08/28 07:21:15 gdamore Exp $ */
|
||||
/*
|
||||
* Copyright (c) 2006 Urbana-Champaign Independent Media Center.
|
||||
* Copyright (c) 2006 Garrett D'Amore.
|
||||
@ -41,7 +41,7 @@
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__KERNEL_RCSID(0, "$NetBSD: arbus.c,v 1.8 2006/07/13 21:38:24 gdamore Exp $");
|
||||
__KERNEL_RCSID(0, "$NetBSD: arbus.c,v 1.9 2006/08/28 07:21:15 gdamore Exp $");
|
||||
|
||||
#include "locators.h"
|
||||
#include <sys/param.h>
|
||||
@ -52,7 +52,7 @@ __KERNEL_RCSID(0, "$NetBSD: arbus.c,v 1.8 2006/07/13 21:38:24 gdamore Exp $");
|
||||
|
||||
#define _MIPS_BUS_DMA_PRIVATE
|
||||
#include <machine/bus.h>
|
||||
#include <mips/atheros/include/ar531xreg.h>
|
||||
#include <mips/atheros/include/ar5312reg.h>
|
||||
#include <mips/atheros/include/ar531xvar.h>
|
||||
#include <mips/atheros/include/arbusvar.h>
|
||||
|
||||
@ -96,59 +96,59 @@ static struct {
|
||||
} arbus_devices[] = {
|
||||
{
|
||||
"ae",
|
||||
AR531X_ENET0_BASE,
|
||||
AR5312_ENET0_BASE,
|
||||
ARBUS_IRQ_ENET0,
|
||||
AR531X_BOARD_CONFIG_ENET0,
|
||||
AR531X_RESET_ENET0 | AR531X_RESET_PHY0,
|
||||
AR531X_ENABLE_ENET0
|
||||
AR5312_BOARD_CONFIG_ENET0,
|
||||
AR5312_RESET_ENET0 | AR5312_RESET_PHY0,
|
||||
AR5312_ENABLE_ENET0
|
||||
},
|
||||
{
|
||||
"ae",
|
||||
AR531X_ENET1_BASE,
|
||||
AR5312_ENET1_BASE,
|
||||
ARBUS_IRQ_ENET1,
|
||||
AR531X_BOARD_CONFIG_ENET1,
|
||||
AR531X_RESET_ENET1 | AR531X_RESET_PHY1,
|
||||
AR531X_ENABLE_ENET1
|
||||
AR5312_BOARD_CONFIG_ENET1,
|
||||
AR5312_RESET_ENET1 | AR5312_RESET_PHY1,
|
||||
AR5312_ENABLE_ENET1
|
||||
},
|
||||
{
|
||||
"com",
|
||||
AR531X_UART0_BASE,
|
||||
AR5312_UART0_BASE,
|
||||
ARBUS_IRQ_UART0,
|
||||
AR531X_BOARD_CONFIG_UART0,
|
||||
AR5312_BOARD_CONFIG_UART0,
|
||||
0,
|
||||
0,
|
||||
},
|
||||
{
|
||||
"com",
|
||||
AR531X_UART1_BASE,
|
||||
AR5312_UART1_BASE,
|
||||
-1,
|
||||
AR531X_BOARD_CONFIG_UART1,
|
||||
AR5312_BOARD_CONFIG_UART1,
|
||||
0,
|
||||
0,
|
||||
},
|
||||
{
|
||||
"ath",
|
||||
AR531X_WLAN0_BASE,
|
||||
AR5312_WLAN0_BASE,
|
||||
ARBUS_IRQ_WLAN0,
|
||||
AR531X_BOARD_CONFIG_WLAN0,
|
||||
AR531X_RESET_WLAN0 |
|
||||
AR531X_RESET_WARM_WLAN0_MAC |
|
||||
AR531X_RESET_WARM_WLAN0_BB,
|
||||
AR531X_ENABLE_WLAN0
|
||||
AR5312_BOARD_CONFIG_WLAN0,
|
||||
AR5312_RESET_WLAN0 |
|
||||
AR5312_RESET_WARM_WLAN0_MAC |
|
||||
AR5312_RESET_WARM_WLAN0_BB,
|
||||
AR5312_ENABLE_WLAN0
|
||||
},
|
||||
{
|
||||
"ath",
|
||||
AR531X_WLAN1_BASE,
|
||||
AR5312_WLAN1_BASE,
|
||||
ARBUS_IRQ_WLAN1,
|
||||
AR531X_BOARD_CONFIG_WLAN1,
|
||||
AR531X_RESET_WLAN1 |
|
||||
AR531X_RESET_WARM_WLAN1_MAC |
|
||||
AR531X_RESET_WARM_WLAN1_BB,
|
||||
AR531X_ENABLE_WLAN1
|
||||
AR5312_BOARD_CONFIG_WLAN1,
|
||||
AR5312_RESET_WLAN1 |
|
||||
AR5312_RESET_WARM_WLAN1_MAC |
|
||||
AR5312_RESET_WARM_WLAN1_BB,
|
||||
AR5312_ENABLE_WLAN1
|
||||
},
|
||||
{
|
||||
"athflash",
|
||||
AR531X_FLASH_BASE,
|
||||
AR5312_FLASH_BASE,
|
||||
-1,
|
||||
0,
|
||||
0,
|
||||
@ -156,7 +156,7 @@ static struct {
|
||||
},
|
||||
{
|
||||
"argpio",
|
||||
AR531X_GPIO_BASE,
|
||||
AR5312_GPIO_BASE,
|
||||
ARBUS_IRQ_GPIO,
|
||||
0,
|
||||
0,
|
||||
@ -211,25 +211,25 @@ arbus_attach(struct device *parent, struct device *self, void *aux)
|
||||
aa.aa_irq = arbus_devices[i].irq;
|
||||
aa.aa_addr = arbus_devices[i].addr;
|
||||
|
||||
if (aa.aa_addr < AR531X_UART0_BASE)
|
||||
if (aa.aa_addr < AR5312_UART0_BASE)
|
||||
aa.aa_size = 0x00100000;
|
||||
else if (aa.aa_addr < AR531X_FLASH_BASE)
|
||||
else if (aa.aa_addr < AR5312_FLASH_BASE)
|
||||
aa.aa_size = 0x1000;
|
||||
|
||||
locs[ARBUSCF_ADDR] = aa.aa_addr;
|
||||
|
||||
if (arbus_devices[i].reset) {
|
||||
/* put device into reset */
|
||||
PUTSYSREG(AR531X_SYSREG_RESETCTL,
|
||||
GETSYSREG(AR531X_SYSREG_RESETCTL) |
|
||||
PUTSYSREG(AR5312_SYSREG_RESETCTL,
|
||||
GETSYSREG(AR5312_SYSREG_RESETCTL) |
|
||||
arbus_devices[i].reset);
|
||||
|
||||
/* this could probably be a tsleep */
|
||||
delay(15000);
|
||||
|
||||
/* take it out of reset */
|
||||
PUTSYSREG(AR531X_SYSREG_RESETCTL,
|
||||
GETSYSREG(AR531X_SYSREG_RESETCTL) &
|
||||
PUTSYSREG(AR5312_SYSREG_RESETCTL,
|
||||
GETSYSREG(AR5312_SYSREG_RESETCTL) &
|
||||
~arbus_devices[i].reset);
|
||||
|
||||
delay(25);
|
||||
@ -237,8 +237,8 @@ arbus_attach(struct device *parent, struct device *self, void *aux)
|
||||
|
||||
if (arbus_devices[i].enable) {
|
||||
/* enable it */
|
||||
PUTSYSREG(AR531X_SYSREG_ENABLE,
|
||||
GETSYSREG(AR531X_SYSREG_ENABLE) |
|
||||
PUTSYSREG(AR5312_SYSREG_ENABLE,
|
||||
GETSYSREG(AR5312_SYSREG_ENABLE) |
|
||||
arbus_devices[i].enable);
|
||||
}
|
||||
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: argpio.c,v 1.1 2006/07/07 22:03:19 gdamore Exp $ */
|
||||
/* $NetBSD: argpio.c,v 1.2 2006/08/28 07:21:15 gdamore Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 2006 Garrett D'Amore
|
||||
@ -32,7 +32,7 @@
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__KERNEL_RCSID(0, "$NetBSD: argpio.c,v 1.1 2006/07/07 22:03:19 gdamore Exp $");
|
||||
__KERNEL_RCSID(0, "$NetBSD: argpio.c,v 1.2 2006/08/28 07:21:15 gdamore Exp $");
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/conf.h>
|
||||
@ -44,7 +44,7 @@ __KERNEL_RCSID(0, "$NetBSD: argpio.c,v 1.1 2006/07/07 22:03:19 gdamore Exp $");
|
||||
#include <machine/bus.h>
|
||||
#include <machine/intr.h>
|
||||
|
||||
#include <mips/atheros/include/ar531xreg.h>
|
||||
#include <mips/atheros/include/ar5312reg.h>
|
||||
#include <mips/atheros/include/ar531xvar.h>
|
||||
#include <mips/atheros/include/arbusvar.h>
|
||||
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $Id: com_arbus.c,v 1.2 2006/07/13 22:56:01 gdamore Exp $ */
|
||||
/* $Id: com_arbus.c,v 1.3 2006/08/28 07:21:15 gdamore Exp $ */
|
||||
/*-
|
||||
* Copyright (c) 2006 Urbana-Champaign Independent Media Center.
|
||||
* Copyright (c) 2006 Garrett D'Amore.
|
||||
@ -108,7 +108,7 @@
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__KERNEL_RCSID(0, "$NetBSD: com_arbus.c,v 1.2 2006/07/13 22:56:01 gdamore Exp $");
|
||||
__KERNEL_RCSID(0, "$NetBSD: com_arbus.c,v 1.3 2006/08/28 07:21:15 gdamore Exp $");
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
@ -125,7 +125,7 @@ __KERNEL_RCSID(0, "$NetBSD: com_arbus.c,v 1.2 2006/07/13 22:56:01 gdamore Exp $"
|
||||
|
||||
#include <mips/cpuregs.h>
|
||||
#include <mips/atheros/include/arbusvar.h>
|
||||
#include <mips/atheros/include/ar531xreg.h>
|
||||
#include <mips/atheros/include/ar531xvar.h>
|
||||
|
||||
struct com_arbus_softc {
|
||||
struct com_softc sc_com;
|
||||
@ -193,7 +193,7 @@ com_arbus_attach(struct device *parent, struct device *self, void *aux)
|
||||
struct arbus_attach_args *aa = aux;
|
||||
bus_space_handle_t ioh;
|
||||
|
||||
sc->sc_frequency = curcpu()->ci_cpu_freq / 4;
|
||||
sc->sc_frequency = ar531x_sys_freq();
|
||||
|
||||
if (!com_is_console(aa->aa_bst, aa->aa_addr, &ioh) &&
|
||||
bus_space_map(aa->aa_bst, aa->aa_addr, aa->aa_size, 0,
|
||||
@ -229,7 +229,6 @@ void
|
||||
com_arbus_cnattach(bus_addr_t addr)
|
||||
{
|
||||
struct com_regs regs;
|
||||
uint32_t sysfreq;
|
||||
|
||||
regs.cr_iot = arbus_get_bus_space_tag();
|
||||
regs.cr_iobase = addr;
|
||||
@ -240,8 +239,7 @@ com_arbus_cnattach(bus_addr_t addr)
|
||||
®s.cr_ioh))
|
||||
return;
|
||||
|
||||
sysfreq = curcpu()->ci_cpu_freq / 4;
|
||||
|
||||
comcnattach1(®s, com_arbus_baud, sysfreq, COM_TYPE_NORMAL, CONMODE);
|
||||
comcnattach1(®s, com_arbus_baud, ar531x_sys_freq(),
|
||||
COM_TYPE_NORMAL, CONMODE);
|
||||
}
|
||||
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: if_ath_arbus.c,v 1.5 2006/07/14 13:37:25 seanb Exp $ */
|
||||
/* $NetBSD: if_ath_arbus.c,v 1.6 2006/08/28 07:21:15 gdamore Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 2006 Jared D. McNeill <jmcneill@invisible.ca>
|
||||
@ -34,7 +34,7 @@
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__KERNEL_RCSID(0, "$NetBSD: if_ath_arbus.c,v 1.5 2006/07/14 13:37:25 seanb Exp $");
|
||||
__KERNEL_RCSID(0, "$NetBSD: if_ath_arbus.c,v 1.6 2006/08/28 07:21:15 gdamore Exp $");
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
@ -58,7 +58,7 @@ __KERNEL_RCSID(0, "$NetBSD: if_ath_arbus.c,v 1.5 2006/07/14 13:37:25 seanb Exp $
|
||||
#include <net80211/ieee80211_netbsd.h>
|
||||
#include <net80211/ieee80211_var.h>
|
||||
|
||||
#include <mips/atheros/include/ar531xreg.h>
|
||||
#include <mips/atheros/include/ar5312reg.h>
|
||||
#include <mips/atheros/include/ar531xvar.h>
|
||||
#include <mips/atheros/include/arbusvar.h>
|
||||
|
||||
@ -111,8 +111,8 @@ ath_arbus_attach(struct device *parent, struct device *self, void *opaque)
|
||||
sc = &asc->sc_ath;
|
||||
aa = (struct arbus_attach_args *)opaque;
|
||||
|
||||
rev = GETSYSREG(AR531X_SYSREG_REVISION);
|
||||
devid = AR531X_REVISION_WMAC(rev);
|
||||
rev = GETSYSREG(AR5312_SYSREG_REVISION);
|
||||
devid = AR5312_REVISION_WMAC(rev);
|
||||
name = ath_hal_probe(PCI_VENDOR_ATHEROS, devid);
|
||||
|
||||
printf(": %s\n", name ? name : "Unknown AR531X WLAN");
|
||||
|
||||
213
sys/arch/mips/atheros/include/ar5312reg.h
Normal file
213
sys/arch/mips/atheros/include/ar5312reg.h
Normal file
@ -0,0 +1,213 @@
|
||||
/* $Id: ar5312reg.h,v 1.1 2006/08/28 07:21:15 gdamore Exp $ */
|
||||
/*
|
||||
* Copyright (c) 2006 Urbana-Champaign Independent Media Center.
|
||||
* Copyright (c) 2006 Garrett D'Amore.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This code was written by Garrett D'Amore for the Champaign-Urbana
|
||||
* Community Wireless Network Project.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or
|
||||
* without modification, are permitted provided that the following
|
||||
* conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above
|
||||
* copyright notice, this list of conditions and the following
|
||||
* disclaimer in the documentation and/or other materials provided
|
||||
* with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this
|
||||
* software must display the following acknowledgements:
|
||||
* This product includes software developed by the Urbana-Champaign
|
||||
* Independent Media Center.
|
||||
* This product includes software developed by Garrett D'Amore.
|
||||
* 4. Urbana-Champaign Independent Media Center's name and Garrett
|
||||
* D'Amore's name may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE URBANA-CHAMPAIGN INDEPENDENT
|
||||
* MEDIA CENTER AND GARRETT D'AMORE ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE URBANA-CHAMPAIGN INDEPENDENT
|
||||
* MEDIA CENTER OR GARRETT D'AMORE BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
|
||||
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _MIPS_ATHEROS_AR5312REG_H_
|
||||
#define _MIPS_ATHEROS_AR5312REG_H_
|
||||
|
||||
#define AR5312_MEM0_BASE 0x00000000 /* sdram */
|
||||
#define AR5312_MEM1_BASE 0x08000000 /* sdram/flash */
|
||||
#define AR5312_MEM3_BASE 0x10000000 /* flash */
|
||||
#define AR5312_WLAN0_BASE 0x18000000
|
||||
#define AR5312_ENET0_BASE 0x18100000
|
||||
#define AR5312_ENET1_BASE 0x18200000
|
||||
#define AR5312_SDRAMCTL_BASE 0x18300000
|
||||
#define AR5312_FLASHCTL_BASE 0x18400000
|
||||
#define AR5312_WLAN1_BASE 0x18500000
|
||||
#define AR5312_UART0_BASE 0x1C000000 /* high speed */
|
||||
#define AR5312_UART1_BASE 0x1C001000
|
||||
#define AR5312_GPIO_BASE 0x1C002000
|
||||
#define AR5312_SYSREG_BASE 0x1C003000
|
||||
#define AR5312_UARTDMA_BASE 0x1C004000
|
||||
#define AR5312_FLASH_BASE 0x1E000000
|
||||
#define AR5312_FLASH_END 0x20000000 /* possibly aliased */
|
||||
|
||||
/*
|
||||
* FLASHCTL registers -- offset relative to AR531X_FLASHCTL_BASE
|
||||
*/
|
||||
#define AR5312_FLASHCTL_0 0x00
|
||||
#define AR5312_FLASHCTL_1 0x04
|
||||
#define AR5312_FLASHCTL_2 0x08
|
||||
|
||||
#define AR5312_FLASHCTL_IDCY_MASK 0xf /* idle cycle turn */
|
||||
#define AR5312_FLASHCTL_IDCY_SHIFT 0
|
||||
#define AR5312_FLASHCTL_WST1_MASK 0x3e0 /* wait state 1 */
|
||||
#define AR5312_FLASHCTL_WST1_SHIFT 5
|
||||
#define AR5312_FLASHCTL_WST2_MASK 0xf800 /* wait state 1 */
|
||||
#define AR5312_FLASHCTL_WST2_SHIFT 11
|
||||
#define AR5312_FLASHCTL_RBLE 0x00000400 /* rd byte enable */
|
||||
#define AR5312_FLASHCTL_AC_MASK 0x00070000 /* addr chk */
|
||||
#define AR5312_FLASHCTL_AC_SHIFT 16
|
||||
#define AR5312_FLASHCTL_AC_128K 0x00000000
|
||||
#define AR5312_FLASHCTL_AC_256K 0x00010000
|
||||
#define AR5312_FLASHCTL_AC_512K 0x00020000
|
||||
#define AR5312_FLASHCTL_AC_1M 0x00030000
|
||||
#define AR5312_FLASHCTL_AC_2M 0x00040000
|
||||
#define AR5312_FLASHCTL_AC_4M 0x00050000
|
||||
#define AR5312_FLASHCTL_AC_8M 0x00060000
|
||||
#define AR5312_FLASHCTL_AC_16M 0x00070000
|
||||
#define AR5312_FLASHCTL_E 0x00080000 /* enable */
|
||||
#define AR5312_FLASHCTL_MW_MASK 0x30000000 /* mem width */
|
||||
|
||||
/*
|
||||
* SYSREG registers -- offset relative to AR531X_SYSREG_BASE
|
||||
*/
|
||||
#define AR5312_SYSREG_TIMER 0x0000
|
||||
#define AR5312_SYSREG_TIMER_RELOAD 0x0004
|
||||
#define AR5312_SYSREG_WDOG_CTL 0x0008
|
||||
#define AR5312_SYSREG_WDOG_TIMER 0x000c
|
||||
#define AR5312_SYSREG_MISC_INTSTAT 0x0010
|
||||
#define AR5312_SYSREG_MISC_INTMASK 0x0014
|
||||
#define AR5312_SYSREG_INTSTAT 0x0018
|
||||
#define AR5312_SYSREG_RESETCTL 0x0020
|
||||
#define AR5312_SYSREG_CLOCKCTL 0x0064
|
||||
#define AR5312_SYSREG_SCRATCH 0x006c
|
||||
#define AR5312_SYSREG_AHBPERR 0x0070
|
||||
#define AR5312_SYSREG_AHBDMAE 0x0078
|
||||
#define AR5312_SYSREG_ENABLE 0x0080
|
||||
#define AR5312_SYSREG_REVISION 0x0090
|
||||
|
||||
/* WDOG_CTL watchdog control bits */
|
||||
#define AR5312_WDOG_CTL_IGNORE 0x0000
|
||||
#define AR5312_WDOG_CTL_NMI 0x0001
|
||||
#define AR5312_WDOG_CTL_RESET 0x0002
|
||||
|
||||
/* Resets */
|
||||
#define AR5312_RESET_SYSTEM 0x00000001
|
||||
#define AR5312_RESET_CPU 0x00000002
|
||||
#define AR5312_RESET_WLAN0 0x00000004 /* mac & bb */
|
||||
#define AR5312_RESET_PHY0 0x00000008 /* enet phy */
|
||||
#define AR5312_RESET_PHY1 0x00000010 /* enet phy */
|
||||
#define AR5312_RESET_ENET0 0x00000020 /* mac */
|
||||
#define AR5312_RESET_ENET1 0x00000040 /* mac */
|
||||
#define AR5312_RESET_UART0 0x00000100 /* mac */
|
||||
#define AR5312_RESET_WLAN1 0x00000200 /* mac & bb */
|
||||
#define AR5312_RESET_APB 0x00000400 /* bridge */
|
||||
#define AR5312_RESET_WARM_CPU 0x00001000
|
||||
#define AR5312_RESET_WARM_WLAN0_MAC 0x00002000
|
||||
#define AR5312_RESET_WARM_WLAN0_BB 0x00004000
|
||||
#define AR5312_RESET_NMI 0x00010000
|
||||
#define AR5312_RESET_WARM_WLAN1_MAC 0x00020000
|
||||
#define AR5312_RESET_WARM_WLAN1_BB 0x00040000
|
||||
#define AR5312_RESET_LOCAL_BUS 0x00080000
|
||||
#define AR5312_RESET_WDOG 0x00100000
|
||||
|
||||
/* AR5312/2312 clockctl bits */
|
||||
#define AR5312_CLOCKCTL_PREDIVIDE_MASK 0x00000030
|
||||
#define AR5312_CLOCKCTL_PREDIVIDE_SHIFT 4
|
||||
#define AR5312_CLOCKCTL_MULTIPLIER_MASK 0x00001f00
|
||||
#define AR5312_CLOCKCTL_MULTIPLIER_SHIFT 8
|
||||
#define AR5312_CLOCKCTL_DOUBLER_MASK 0x00010000
|
||||
|
||||
/* AR2313 clockctl */
|
||||
#define AR2313_CLOCKCTL_PREDIVIDE_MASK 0x00003000
|
||||
#define AR2313_CLOCKCTL_PREDIVIDE_SHIFT 12
|
||||
#define AR2313_CLOCKCTL_MULTIPLIER_MASK 0x001f0000
|
||||
#define AR2313_CLOCKCTL_MULTIPLIER_SHIFT 16
|
||||
#define AR2313_CLOCKCTL_DOUBLER_MASK 0x00000000
|
||||
|
||||
/* Enables */
|
||||
#define AR5312_ENABLE_WLAN0 0x0001
|
||||
#define AR5312_ENABLE_ENET0 0x0002
|
||||
#define AR5312_ENABLE_ENET1 0x0004
|
||||
#define AR5312_ENABLE_WLAN1 0x0018 /* both DMA and PIO */
|
||||
|
||||
/* Revision ids */
|
||||
#define AR5312_REVISION_WMAC_MAJOR(x) (((x) >> 12) & 0xf)
|
||||
#define AR5312_REVISION_WMAC_MINOR(x) (((x) >> 8) & 0xf)
|
||||
#define AR5312_REVISION_WMAC(x) (((x) >> 8) & 0xff)
|
||||
#define AR5312_REVISION_MAJOR(x) (((x) >> 4) & 0xf)
|
||||
#define AR5312_REVISION_MINOR(x) (((x) >> 0) & 0xf)
|
||||
|
||||
#define AR5312_REVISION_MAJ_AR5311 0x1
|
||||
#define AR5312_REVISION_MAJ_AR5312 0x4
|
||||
#define AR5312_REVISION_MAJ_AR2313 0x5
|
||||
#define AR5312_REVISION_MAJ_AR5315 0xB
|
||||
|
||||
/*
|
||||
* SDRAMCTL registers -- offset relative to SDRAMCTL
|
||||
*/
|
||||
#define AR5312_SDRAMCTL_MEM_CFG0 0x0000
|
||||
#define AR5312_SDRAMCTL_MEM_CFG1 0x0004
|
||||
|
||||
/* memory config 1 bits */
|
||||
#define AR5312_MEM_CFG1_BANK0_MASK 0x00000700
|
||||
#define AR5312_MEM_CFG1_BANK0_SHIFT 8
|
||||
#define AR5312_MEM_CFG1_BANK1_MASK 0x00007000
|
||||
#define AR5312_MEM_CFG1_BANK1_SHIFT 12
|
||||
|
||||
/* helper macro for accessing system registers without bus space */
|
||||
#define REGVAL(x) *((volatile uint32_t *)(MIPS_PHYS_TO_KSEG1((x))))
|
||||
#define GETSYSREG(x) REGVAL((x) + AR5312_SYSREG_BASE)
|
||||
#define PUTSYSREG(x,v) (REGVAL((x) + AR5312_SYSREG_BASE)) = (v)
|
||||
#define GETSDRAMREG(x) REGVAL((x) + AR5312_SDRAMCTL_BASE)
|
||||
#define PUTSDRAMREG(x,v) (REGVAL((x) + AR5312_SDRAMCTL_BASE)) = (v)
|
||||
|
||||
/*
|
||||
* Board data. This is located in flash somewhere, ar531x_board_info
|
||||
* locates it.
|
||||
*/
|
||||
#include <contrib/dev/ath/ah_soc.h> /* XXX really doesn't belong in hal */
|
||||
|
||||
/* XXX write-around for now */
|
||||
#define AR5312_BOARD_MAGIC AR531X_BD_MAGIC
|
||||
|
||||
/* config bits */
|
||||
#define AR5312_BOARD_CONFIG_ENET0 BD_ENET0
|
||||
#define AR5312_BOARD_CONFIG_ENET1 BD_ENET1
|
||||
#define AR5312_BOARD_CONFIG_UART1 BD_UART1
|
||||
#define AR5312_BOARD_CONFIG_UART0 BD_UART0
|
||||
#define AR5312_BOARD_CONFIG_RSTFACTORY BD_RSTFACTORY
|
||||
#define AR5312_BOARD_CONFIG_SYSLED BD_SYSLED
|
||||
#define AR5312_BOARD_CONFIG_EXTUARTCLK BD_EXTUARTCLK
|
||||
#define AR5312_BOARD_CONFIG_CPUFREQ BD_CPUFREQ
|
||||
#define AR5312_BOARD_CONFIG_SYSFREQ BD_SYSFREQ
|
||||
#define AR5312_BOARD_CONFIG_WLAN0 BD_WLAN0
|
||||
#define AR5312_BOARD_CONFIG_MEMCAP BD_MEMCAP
|
||||
#define AR5312_BOARD_CONFIG_DISWDOG BD_DISWATCHDOG
|
||||
#define AR5312_BOARD_CONFIG_WLAN1 BD_WLAN1
|
||||
#define AR5312_BOARD_CONFIG_AR2312 BD_ISCASPER
|
||||
#define AR5312_BOARD_CONFIG_WLAN0_2G BD_WLAN0_2G_EN
|
||||
#define AR5312_BOARD_CONFIG_WLAN0_5G BD_WLAN0_5G_EN
|
||||
#define AR5312_BOARD_CONFIG_WLAN1_2G BD_WLAN1_2G_EN
|
||||
#define AR5312_BOARD_CONFIG_WLAN1_5G BD_WLAN1_5G_EN
|
||||
|
||||
#endif /* _MIPS_ATHEROS_AR531XREG_H_ */
|
||||
@ -1,214 +0,0 @@
|
||||
/* $Id: ar531xreg.h,v 1.4 2006/06/09 18:35:42 gdamore Exp $ */
|
||||
/*
|
||||
* Copyright (c) 2006 Urbana-Champaign Independent Media Center.
|
||||
* Copyright (c) 2006 Garrett D'Amore.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This code was written by Garrett D'Amore for the Champaign-Urbana
|
||||
* Community Wireless Network Project.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or
|
||||
* without modification, are permitted provided that the following
|
||||
* conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above
|
||||
* copyright notice, this list of conditions and the following
|
||||
* disclaimer in the documentation and/or other materials provided
|
||||
* with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this
|
||||
* software must display the following acknowledgements:
|
||||
* This product includes software developed by the Urbana-Champaign
|
||||
* Independent Media Center.
|
||||
* This product includes software developed by Garrett D'Amore.
|
||||
* 4. Urbana-Champaign Independent Media Center's name and Garrett
|
||||
* D'Amore's name may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE URBANA-CHAMPAIGN INDEPENDENT
|
||||
* MEDIA CENTER AND GARRETT D'AMORE ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE URBANA-CHAMPAIGN INDEPENDENT
|
||||
* MEDIA CENTER OR GARRETT D'AMORE BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
|
||||
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _MIPS_ATHEROS_AR531XREG_H_
|
||||
#define _MIPS_ATHEROS_AR531XREG_H_
|
||||
|
||||
#define AR531X_MEM0_BASE 0x00000000 /* sdram */
|
||||
#define AR531X_MEM1_BASE 0x08000000 /* sdram/flash */
|
||||
#define AR531X_MEM3_BASE 0x10000000 /* flash */
|
||||
#define AR531X_WLAN0_BASE 0x18000000
|
||||
#define AR531X_ENET0_BASE 0x18100000
|
||||
#define AR531X_ENET1_BASE 0x18200000
|
||||
#define AR531X_SDRAMCTL_BASE 0x18300000
|
||||
#define AR531X_FLASHCTL_BASE 0x18400000
|
||||
#define AR531X_WLAN1_BASE 0x18500000
|
||||
#define AR531X_UART0_BASE 0x1C000000 /* high speed */
|
||||
#define AR531X_UART1_BASE 0x1C001000
|
||||
#define AR531X_GPIO_BASE 0x1C002000
|
||||
#define AR531X_SYSREG_BASE 0x1C003000
|
||||
#define AR531X_UARTDMA_BASE 0x1C004000
|
||||
#define AR531X_FLASH_BASE 0x1E000000
|
||||
#define AR531X_FLASH_END 0x20000000 /* possibly aliased */
|
||||
|
||||
/*
|
||||
* FLASHCTL registers -- offset relative to AR531X_FLASHCTL_BASE
|
||||
*/
|
||||
#define AR531X_FLASHCTL_0 0x00
|
||||
#define AR531X_FLASHCTL_1 0x04
|
||||
#define AR531X_FLASHCTL_2 0x08
|
||||
|
||||
#define AR531X_FLASHCTL_IDCY_MASK 0xf /* idle cycle turn */
|
||||
#define AR531X_FLASHCTL_IDCY_SHIFT 0
|
||||
#define AR531X_FLASHCTL_WST1_MASK 0x3e0 /* wait state 1 */
|
||||
#define AR531X_FLASHCTL_WST1_SHIFT 5
|
||||
#define AR531X_FLASHCTL_WST2_MASK 0xf800 /* wait state 1 */
|
||||
#define AR531X_FLASHCTL_WST2_SHIFT 11
|
||||
#define AR531X_FLASHCTL_RBLE 0x00000400 /* rd byte enable */
|
||||
#define AR531X_FLASHCTL_AC_MASK 0x00070000 /* addr chk */
|
||||
#define AR531X_FLASHCTL_AC_SHIFT 16
|
||||
#define AR531X_FLASHCTL_AC_128K 0x00000000
|
||||
#define AR531X_FLASHCTL_AC_256K 0x00010000
|
||||
#define AR531X_FLASHCTL_AC_512K 0x00020000
|
||||
#define AR531X_FLASHCTL_AC_1M 0x00030000
|
||||
#define AR531X_FLASHCTL_AC_2M 0x00040000
|
||||
#define AR531X_FLASHCTL_AC_4M 0x00050000
|
||||
#define AR531X_FLASHCTL_AC_8M 0x00060000
|
||||
#define AR531X_FLASHCTL_AC_16M 0x00070000
|
||||
#define AR531X_FLASHCTL_E 0x00080000 /* enable */
|
||||
#define AR531X_FLASHCTL_MW_MASK 0x30000000 /* mem width */
|
||||
|
||||
/*
|
||||
* SYSREG registers -- offset relative to AR531X_SYSREG_BASE
|
||||
*/
|
||||
#define AR531X_SYSREG_TIMER 0x0000
|
||||
#define AR531X_SYSREG_TIMER_RELOAD 0x0004
|
||||
#define AR531X_SYSREG_WDOG_CTL 0x0008
|
||||
#define AR531X_SYSREG_WDOG_TIMER 0x000c
|
||||
#define AR531X_SYSREG_MISC_INTSTAT 0x0010
|
||||
#define AR531X_SYSREG_MISC_INTMASK 0x0014
|
||||
#define AR531X_SYSREG_INTSTAT 0x0018
|
||||
#define AR531X_SYSREG_RESETCTL 0x0020
|
||||
#define AR531X_SYSREG_CLOCKCTL 0x0064
|
||||
#define AR531X_SYSREG_SCRATCH 0x006c
|
||||
#define AR531X_SYSREG_AHBPERR 0x0070
|
||||
#define AR531X_SYSREG_AHBDMAE 0x0078
|
||||
#define AR531X_SYSREG_ENABLE 0x0080
|
||||
#define AR531X_SYSREG_REVISION 0x0090
|
||||
|
||||
/* WDOG_CTL watchdog control bits */
|
||||
#define AR531X_WDOG_CTL_IGNORE 0x0000
|
||||
#define AR531X_WDOG_CTL_NMI 0x0001
|
||||
#define AR531X_WDOG_CTL_RESET 0x0002
|
||||
|
||||
/* Resets */
|
||||
#define AR531X_RESET_SYSTEM 0x00000001
|
||||
#define AR531X_RESET_CPU 0x00000002
|
||||
#define AR531X_RESET_WLAN0 0x00000004 /* mac & bb */
|
||||
#define AR531X_RESET_PHY0 0x00000008 /* enet phy */
|
||||
#define AR531X_RESET_PHY1 0x00000010 /* enet phy */
|
||||
#define AR531X_RESET_ENET0 0x00000020 /* mac */
|
||||
#define AR531X_RESET_ENET1 0x00000040 /* mac */
|
||||
#define AR531X_RESET_UART0 0x00000100 /* mac */
|
||||
#define AR531X_RESET_WLAN1 0x00000200 /* mac & bb */
|
||||
#define AR531X_RESET_APB 0x00000400 /* bridge */
|
||||
#define AR531X_RESET_WARM_CPU 0x00001000
|
||||
#define AR531X_RESET_WARM_WLAN0_MAC 0x00002000
|
||||
#define AR531X_RESET_WARM_WLAN0_BB 0x00004000
|
||||
#define AR531X_RESET_NMI 0x00010000
|
||||
#define AR531X_RESET_WARM_WLAN1_MAC 0x00020000
|
||||
#define AR531X_RESET_WARM_WLAN1_BB 0x00040000
|
||||
#define AR531X_RESET_LOCAL_BUS 0x00080000
|
||||
#define AR531X_RESET_WDOG 0x00100000
|
||||
|
||||
/* AR5312/2312 clockctl bits */
|
||||
#define AR5312_CLOCKCTL_PREDIVIDE_MASK 0x00000030
|
||||
#define AR5312_CLOCKCTL_PREDIVIDE_SHIFT 4
|
||||
#define AR5312_CLOCKCTL_MULTIPLIER_MASK 0x00001f00
|
||||
#define AR5312_CLOCKCTL_MULTIPLIER_SHIFT 8
|
||||
#define AR5312_CLOCKCTL_DOUBLER_MASK 0x00010000
|
||||
|
||||
/* AR2313 clockctl */
|
||||
#define AR2313_CLOCKCTL_PREDIVIDE_MASK 0x00003000
|
||||
#define AR2313_CLOCKCTL_PREDIVIDE_SHIFT 12
|
||||
#define AR2313_CLOCKCTL_MULTIPLIER_MASK 0x001f0000
|
||||
#define AR2313_CLOCKCTL_MULTIPLIER_SHIFT 16
|
||||
#define AR2313_CLOCKCTL_DOUBLER_MASK 0x00000000
|
||||
|
||||
/* Enables */
|
||||
#define AR531X_ENABLE_WLAN0 0x0001
|
||||
#define AR531X_ENABLE_ENET0 0x0002
|
||||
#define AR531X_ENABLE_ENET1 0x0004
|
||||
#define AR531X_ENABLE_WLAN1 0x0018 /* both DMA and PIO */
|
||||
|
||||
/* Revision ids */
|
||||
#define AR531X_REVISION_WMAC_MAJOR(x) (((x) >> 12) & 0xf)
|
||||
#define AR531X_REVISION_WMAC_MINOR(x) (((x) >> 8) & 0xf)
|
||||
#define AR531X_REVISION_WMAC(x) (((x) >> 8) & 0xff)
|
||||
#define AR531X_REVISION_MAJOR(x) (((x) >> 4) & 0xf)
|
||||
#define AR531X_REVISION_MINOR(x) (((x) >> 0) & 0xf)
|
||||
|
||||
#define AR531X_REVISION_MAJ_AR5312 0x4
|
||||
#define AR531X_REVISION_MAJ_AR2313 0x5
|
||||
|
||||
#define AR531X_REVISION_MIN_DUAL 0x0 /* dual wlan */
|
||||
#define AR531X_REVISION_MIN_SINGLE 0x1 /* single wlan */
|
||||
|
||||
/*
|
||||
* SDRAMCTL registers -- offset relative to SDRAMCTL
|
||||
*/
|
||||
#define AR531X_SDRAMCTL_MEM_CFG0 0x0000
|
||||
#define AR531X_SDRAMCTL_MEM_CFG1 0x0004
|
||||
|
||||
/* memory config 1 bits */
|
||||
#define AR531X_MEM_CFG1_BANK0_MASK 0x00000700
|
||||
#define AR531X_MEM_CFG1_BANK0_SHIFT 8
|
||||
#define AR531X_MEM_CFG1_BANK1_MASK 0x00007000
|
||||
#define AR531X_MEM_CFG1_BANK1_SHIFT 12
|
||||
|
||||
/* helper macro for accessing system registers without bus space */
|
||||
#define REGVAL(x) *((volatile uint32_t *)(MIPS_PHYS_TO_KSEG1((x))))
|
||||
#define GETSYSREG(x) REGVAL((x) + AR531X_SYSREG_BASE)
|
||||
#define PUTSYSREG(x,v) (REGVAL((x) + AR531X_SYSREG_BASE)) = (v)
|
||||
#define GETSDRAMREG(x) REGVAL((x) + AR531X_SDRAMCTL_BASE)
|
||||
#define PUTSDRAMREG(x,v) (REGVAL((x) + AR531X_SDRAMCTL_BASE)) = (v)
|
||||
|
||||
/*
|
||||
* Board data. This is located in flash somewhere, ar531x_board_info
|
||||
* locates it.
|
||||
*/
|
||||
#include <contrib/dev/ath/ah_soc.h> /* XXX really doesn't belong in hal */
|
||||
|
||||
/* XXX write-around for now */
|
||||
#define AR531X_BOARD_MAGIC AR531X_BD_MAGIC
|
||||
|
||||
/* config bits */
|
||||
#define AR531X_BOARD_CONFIG_ENET0 BD_ENET0
|
||||
#define AR531X_BOARD_CONFIG_ENET1 BD_ENET1
|
||||
#define AR531X_BOARD_CONFIG_UART1 BD_UART1
|
||||
#define AR531X_BOARD_CONFIG_UART0 BD_UART0
|
||||
#define AR531X_BOARD_CONFIG_RSTFACTORY BD_RSTFACTORY
|
||||
#define AR531X_BOARD_CONFIG_SYSLED BD_SYSLED
|
||||
#define AR531X_BOARD_CONFIG_EXTUARTCLK BD_EXTUARTCLK
|
||||
#define AR531X_BOARD_CONFIG_CPUFREQ BD_CPUFREQ
|
||||
#define AR531X_BOARD_CONFIG_SYSFREQ BD_SYSFREQ
|
||||
#define AR531X_BOARD_CONFIG_WLAN0 BD_WLAN0
|
||||
#define AR531X_BOARD_CONFIG_MEMCAP BD_MEMCAP
|
||||
#define AR531X_BOARD_CONFIG_DISWDOG BD_DISWATCHDOG
|
||||
#define AR531X_BOARD_CONFIG_WLAN1 BD_WLAN1
|
||||
#define AR531X_BOARD_CONFIG_AR2312 BD_ISCASPER
|
||||
#define AR531X_BOARD_CONFIG_WLAN0_2G BD_WLAN0_2G_EN
|
||||
#define AR531X_BOARD_CONFIG_WLAN0_5G BD_WLAN0_5G_EN
|
||||
#define AR531X_BOARD_CONFIG_WLAN1_2G BD_WLAN1_2G_EN
|
||||
#define AR531X_BOARD_CONFIG_WLAN1_5G BD_WLAN1_5G_EN
|
||||
|
||||
#endif /* _MIPS_ATHEROS_AR531XREG_H_ */
|
||||
@ -1,4 +1,4 @@
|
||||
/* $Id: ar531xvar.h,v 1.2 2006/06/05 05:14:38 gdamore Exp $ */
|
||||
/* $Id: ar531xvar.h,v 1.3 2006/08/28 07:21:15 gdamore Exp $ */
|
||||
/*
|
||||
* Copyright (c) 2006 Urbana-Champaign Independent Media Center.
|
||||
* Copyright (c) 2006 Garrett D'Amore.
|
||||
@ -53,8 +53,20 @@ void ar531x_misc_intr_disestablish(void *);
|
||||
|
||||
void ar531x_cpuintr(uint32_t, uint32_t, uint32_t, uint32_t);
|
||||
|
||||
void ar531x_cal_timer(void);
|
||||
/*
|
||||
* CPU specific routines.
|
||||
*/
|
||||
size_t ar531x_memsize(void);
|
||||
void ar531x_consinit(void);
|
||||
void ar531x_wdog(uint32_t);
|
||||
void ar531x_businit(void);
|
||||
const char *ar531x_cpuname(void);
|
||||
uint32_t ar531x_cpu_freq(void);
|
||||
uint32_t ar531x_sys_freq(void);
|
||||
|
||||
/*
|
||||
* Board specific things.
|
||||
*/
|
||||
struct ar531x_boarddata;
|
||||
const struct ar531x_boarddata *ar531x_board_info(void);
|
||||
const void *ar531x_radio_info(void);
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
# $NetBSD: files.atheros,v 1.4 2006/07/07 22:03:19 gdamore Exp $
|
||||
# $NetBSD: files.atheros,v 1.5 2006/08/28 07:21:15 gdamore Exp $
|
||||
|
||||
file arch/mips/atheros/ar531x_intr.c
|
||||
file arch/mips/atheros/ar531x_timer.c
|
||||
file arch/mips/atheros/ar5312.c
|
||||
file arch/mips/atheros/ar5312_intr.c
|
||||
file arch/mips/atheros/ar531x_board.c
|
||||
|
||||
# Atheros system bus
|
||||
|
||||
Loading…
Reference in New Issue
Block a user