be inserted into ktrace records. The general change has been to replace
"struct proc *" with "struct lwp *" in various function prototypes, pass
the lwp through and use l_proc to get the process pointer when needed.
Bump the kernel rev up to 1.6V
http://mail-index.netbsd.org/source-changes/2003/05/08/0068.html
There were some side-effects that I didn't anticipate, and fixing them
is proving to be more difficult than I thought, do just eject for now.
Maybe one day we can look at this again.
Fixes PR kern/21517.
isa_dmamap_create() calls to their open/close entrypoints. This worked
with some luck, but broke on i386 when _bus_dmamap_create started
to allocate bounce buffers upfront, since memory below 16M may well
not be available when the sound devices is opened for the Nth time.
To fix this, create a new simple interface, isa_drq_alloc/isa_drq_free,
wrappers around already existing bitmask macros. These are expected
to be used before an isa_dmamap_create call, and after an
isa_dmamap_destroy call, respectively. For the sb and ad1848 drivers,
they're deferred until open/close.
All isa_dmamap_create calls can now use BUS_DMA_ALLOCNOW and be done
at attach time.
space is advertised to UVM by making virtual_avail and virtual_end
first-class exported variables by UVM. Machine-dependent code is
responsible for initializing them before main() is called. Anything
that steals KVA must adjust these variables accordingly.
This reduces the number of instances of this info from 3 to 1, and
simplifies the pmap(9) interface by removing the pmap_virtual_space()
function call, and removing two arguments from pmap_steal_memory().
This also eliminates some kludges such as having to burn kernel_map
entries on space used by the kernel and stolen KVA.
This also eliminates use of VM_{MIN,MAX}_KERNEL_ADDRESS from MI code,
this giving MD code greater flexibility over the bounds of the managed
kernel virtual address space if a given port's specific platforms can
vary in this regard (this is especially true of the evb* ports).
breakpoint address before it's used. Currently a no-op on all but sh5.
This is useful on sh5, for example, to mask off the instruction
type encoding in the bottom two address bits, and makes it possible
to do "db> break $rXX" instead of manually munging the address.
by the application, all NetBSD interfaces are made visible, even
if some other feature-test macro (like _POSIX_C_SOURCE) is defined.
<sys/featuretest.h> defined _NETBSD_SOURCE if none of _ANSI_SOURCE,
_POSIX_C_SOURCE and _XOPEN_SOURCE is defined, so as to preserve
existing behaviour.
This has two major advantages:
+ Programs that require non-POSIX facilities but define _POSIX_C_SOURCE
can trivially be overruled by putting -D_NETBSD_SOURCE in their CFLAGS.
+ It makes most of the #ifs simpler, in that they're all now ORs of the
various macros, rather than having checks for (!defined(_ANSI_SOURCE) ||
!defined(_POSIX_C_SOURCE) || !defined(_XOPEN_SOURCE)) all over the place.
I've tried not to change the semantics of the headers in any case where
_NETBSD_SOURCE wasn't defined, but there were some places where the
current semantics were clearly mad, and retaining them was harder than
correcting them. In particular, I've mostly normalised things so that
_ANSI_SOURCE gets you the smallest set of stuff, then _POSIX_C_SOURCE,
_XOPEN_SOURCE and _NETBSD_SOURCE in that order.
Tested by building for vax, encouraged by thorpej, and uncontested in
tech-userlevel for a week.
objects. Clients of the pool_cache API must consistently use
the "paddr" variants or not, otherwise behavior is undefined.
Enable this on Alpha, ARM, MIPS, and x86. Other platforms must
define POOL_VTOPHYS() in the appropriate manner in order to enable
the feature.
Part 1 of a series of simple patches contributed by Wasabi Systems
to improve network performance.
time ago, with small tweaks by me. Since the R5k doesn't do VCE, the pmap
still needs to be whacked for R5kSC CPUs to work correctly, but this is a
start.
In start (noticed after looking for more COP_1_BIT uses, and note
that there are extra nops here but really they don't hurt), and in
MachFPTrap (noticed by ... running regress!).
external cache enable bit -- this allows software to enable or disable the
(external) L2 cache on the R5k and Rm527x and the (external) L3 cache on
the Rm7k. If the (external) cache is disabled, treat it as if there were
no cache for the purposes of the cache setup code.
Also, update sgimips code to use the new name.
possible to use alternate system call tables. This is usefull for
displaying correctly the arguments in Mach binaries traces.
If NULL is given, then the regular systam call table for the process is used.
require flushing (even in the instruction cache handlers). This gives
about a 4% improvement in a "make depend" benchmark.
Mark the SB-1 CPUs as having a fully coherent data cache that only
require flushing in the instruction cache handlers. This gives about
a 5% improvement in a "make depend" benchmark.
handling for phyiscally-indexed caches where the way size is greater than
the page size.
These work fine with pass 1 SB1 cores, so g/c those workarounds.
Much thanks to Chris Demetriou for many suggestions and helping me get
my head around all this.
original system call number, which can be negative for a Mach trap.
We cannot just replace code by realcode, because ktrsyscall uses it as
an index in the system call table, thus crashing the kernel when the
value is negative.
use the index ops at a offset of the page size as well, controlled by
an MIPS64_SB1 check. The SB1 D-cache way size is physically indexed
and twice as big as the page size (4k), so we weren't flushing all the
addresses we needed too.
XXX: This is kinda gross; will be cleaned up and made more generic soon.
There are still other SB1-specific issues to be cleaned up too...
three new files;
sig_machdep.c (from mips_machdep.c)
copy.S and sigcode.S (from locore.S)
- Nuke the local use of struct sigframe, which is now identical to
struct sigcontext, from sendsig() as the consequence of new signal
trampoline.
asm code which can be built easily in old-ABI and new-ABI environemnts.
In old-ABI, they map to t4-t7, and in new-ABI, they map to a4-a7. This
means that t0-t3,ta0-ta3,t8,t9 are available in both ABIs.
Because ta0-ta3 overlap with arg regs (albeit arg slots which are usually
unused), they should be used only if t0-t3,t8,t9 isn't enough.
lukem