Commit Graph

8 Commits

Author SHA1 Message Date
nisimura d116bc4a0d - Make this compilable with MIPS1 or MIPS3 only configuration. 1999-05-28 07:23:38 +00:00
nisimura 58cf81db34 - Change a symbolic name of TLB entrylo from 'PG_M' to 'PG_D' to reflect
processor design.  MIPS 'dirty bit' is not the same as i386 'dirty bit'.
There is a growing concern of misuse in NetBSD/mips.
1999-05-27 01:56:32 +00:00
nisimura 858e67e157 - Complete vm_offset_t purge for mips processor.
- bzero() -> memset() and bcopy() -> memcpy().
- Garbage collection in trap.c and db_interface.c.
1999-01-06 04:11:25 +00:00
mhitch e03cf7a95c Cast mips1-only and mips3-only pfn_to_vad() macros to match the mips1/mips3
merged inline function.  Fixes inconsist printf format usage in trap.c.
1997-06-21 04:10:42 +00:00
mhitch 806f730e87 Remove stray macro definition; didn't hurt for MIPS1 only, but wrong for
MIPS3.
1997-06-17 04:12:38 +00:00
jonathan fef3e76b31 Changes for configuring both MIPS1 and MIPS3, from a merge of
similar design and code by Jason Thorpe and Jonathan Stone.

NOTE: the kernel-stack-switching code and cacheflush() calls in
locore.S still use #ifdef MIPS3 and need more work.

mips/include/cpu.h:
    Add CPUISMIPS3 for run-time tests of what CPU architecture level
    we're running on.

mips/include/locore.h:
    Add declarations of locore cache-size variables for ref/def toolchain.

mips/include/mips1_pte.h:
    mips1 TLB bit definitions.

mips/include/mips3_pte.h:
    mips3 TLB bit definitions.

mips/include/pte.h:
    define accesor macros for TLB bits (e.g., mips_pg_m_bit(),
    that expand to CPU constants if only one CPU arch is configured,
    or to inline functions if both MIPS1 and MIPS3 are configured.

mips/mips/locore_r2000.S:
    Use MIPS1_PG_xxx constants inside mips1-specific code.

mips/mips/locore_r4000.S:
    Use MIPS3_PG_xxx constants inside mips3-specific code.

mips/mips/locore.S:
    Use MIPS1_PG_xxx constants inside mips3-specific code.
    Use MIPS1_PG_xxx constants inside mips1-specific code.
    (Needs more  work!)

mips/mips/{pmap.c,vm_machdep.c,trap.c}, pmax/pmax/machdep.c:
    Use MIPS3_PG_xxx constants inside mips3-specific functions,
         and MIPS1_PG_XXX inside mips1-specific code.
    Otherwise, use mips_pg_XXX_bit() macros where they apply,
    and use "if (CPUISMIPS3) { ... } else {... }" where they don't.

mips/mips/mips_machdep.c:
    Import Michael Hitch's fixes from the pmax locore-init code
    into mips_vector_init().

pmax/pmax/machdep.c:
    Use generic mips_vector_init() locore vector-init function.
1997-06-16 23:41:40 +00:00
mhitch fb6d59052e More merged MIPS1/MIPS3 support. The pte definitions still need work before
they can be support both MIPS1 and MIPS3.
1997-06-15 17:24:22 +00:00
jonathan 6ac1fdec40 Merge mips1 and mips3 pte/pmap code, pass 0;
* Move mips-I pte (TLBlo) definitions from pmax/include/pte.h
      to mips/include/mips1_pte.h

    * Move mips-III pte (TLBlo) definitions from  pica/include/pte.h
      to mips/include/mips3_pte.h

    * Add new mips/include/pte.h, which includes exactly one of
      mips1_pte.h or mips3_pte.h (which still have namespace collisions),
      depending on "options MIPS1" or "options MIPS3". (hack).
      Move soft kvtopte(), ptetovk() definitions to mips/include/pte.h

    * Add macro PTE_TO_PADDR() to hide the different hardware TLB formats
      when mapping from pte to physical address.

   * Add macro PTE_READONLY() to hide lack of SW read-only bit in mips-III
     tlb. (mips1 pmap uses a sw bit in the PTE, mips3 looks up RO bit in
     the kernel pmap.)

   * Use macros (not direct TLB frobbing) in mips/trap.c, to make it
     mips-1/mips-III indepenndet.

    * Change {pmax,pica}/include/pte.h to just do #include <mips/pte.h>.
1996-10-13 09:28:53 +00:00