from Jeff Smith <jeffs@geocast.com>. These are needed to support
-mips2 compilation. With this change, on a QED 5231 we now pass the
paranoia tests, and are successfully using userlands built with -mips2.
use MIPS_TBRPL(). When PTEs are modified, both src and dst TLBs
are invalidated. MIPS3 single TLB entry has paired double PTE
and pagemove() likely walks through multiple pages. The positive
effect of of MachTLBUpdate() or TBRPL() is unclear.
implementation of locore routines between MIPS1 and MIPS3. It's
independent from mips_locore_jumpvec_t which is for cache/TLB
manipulating routines peculiar to processor designs. mips_locore_jumpvec_t
will be replaced with "processor closures" encapsulating implementation
parameters (cpuinfo) and pointers to conventaion routines (cpuops),
eventually.
discard MachTLBUpdate() calls, however, the necessity of TLB entry
modification in such a way is under question because implementation
glitches on ASID management was straightened, those calls can be
sanely removed after all.
contains the values __SIMPLELOCK_LOCKED and __SIMPLELOCK_UNLOCKED, which
replace the old SIMPLELOCK_LOCKED and SIMPLELOCK_UNLOCKED. These files
are also required to supply inline functions __cpu_simple_lock(),
__cpu_simple_lock_try(), and __cpu_simple_unlock() if locking is to be
supported on that platform (i.e. if MULTIPROCESSOR is defined in the
_KERNEL case). Change these functions to take an int * (&alp->lock_data)
rather than the struct simplelock * itself.
These changes make it possible for userland to use the locking primitives
by including <machine/lock.h>.
The brokenness is revealed sporadorically by memory usage on runtime.
- Avoid Vr4100 incompatibilty by making sure to retain default pgMask
value for TLB invalidation routines.
Fix regress/lib/libc/ieeefp/except for MIPS. Newer FPE handling code
did not generate SIGFPE, but always SIGILL. Add this back to the
assembly code. The QED 5231 requests the kernel emulates some of
the conditions that generate an SIGFPE, but when the emulation code
did a ctc1 to fsr with an exception the kernel got a FPE in kernel mode.
Fix this by saving the fp regs earlier, then saving the new FSR in
the context. This allows the FSR value to be seen by the SIGFPE
handler.
Add fp emulation for 8 mips2 fpu instructions to handle exceptions
(round.w.fmt, trunc.w.fmt, ceil.w.fmt, floor.w.fmt). This lets
perl5 run when compiled -mips2.
ASID#0 is reserved for pmap0 shared between proc0 and kthreads,
and every TLB for KSEG2 has G (global) bit to have wildcard match
regardless of the process' ASID. MIPS1 would flush TLBs belong
to user spaces upon ASID generation bump. Change for MIPS3 is
to be done.
uvm_page_init() has completed, add a boolean uvm.page_init_done,
and test against that. Use this same boolean (rather than
pmap_initialized) in pmap_growkernel() to determine if we are
being called via uvm_page_init() to grow the kernel address space.
This fixes a problem on some i386 configurations where pmap_init()
itself was needing to have the kernel page table grown, and since
pmap_initialized was not yet set to TRUE, pmap_growkernel() was
choosing the wrong code path.
Fix tested by Havard Eidnes.
