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1438 Commits

Author SHA1 Message Date
christos a2dfb1b570 PR/3012: Greg A. Woods: Write all float.h files [except the vax of course] 
in terms of float_ieee.h
 2003-04-19 23:05:28 +00:00
nathanw ff28c51cc0 Make cpu_getmcontext() run the PC through ras_lookup() so that kernel 
getcontext() plus userlevel setcontext() (as used in libpthread) respects
the atomicity of RAS regions.
 2003-04-11 22:02:28 +00:00
simonb 0cdf56e3e6 Fix a tyop in a comment. 2003-04-11 06:24:59 +00:00
thorpej 9bd03b1f69 Cast the arg to MIPS_KSEG0_TO_PHYS() in POOL_VTOPHYS() (thanks, nathan!). 2003-04-09 22:10:58 +00:00
thorpej a0aee79a1d Add the ability for pool caches to cache the physical address of 
objects.  Clients of the pool_cache API must consistently use
the "paddr" variants or not, otherwise behavior is undefined.

Enable this on Alpha, ARM, MIPS, and x86.  Other platforms must
define POOL_VTOPHYS() in the appropriate manner in order to enable
the feature.

Part 1 of a series of simple patches contributed by Wasabi Systems
to improve network performance.
 2003-04-09 18:22:13 +00:00
thorpej cf9d21bf8e Use PAGE_SIZE rather than NBPG. 2003-04-08 23:39:14 +00:00
hpeyerl 5eefd45be5 Read USBH_ENABLE twice in succession according to Errata 7 for au1500. 2003-04-03 16:41:23 +00:00
thorpej cc2c493bc4 Use PAGE_SIZE rather than NBPG. 2003-04-02 07:35:54 +00:00
thorpej bc226765c8 Use PAGE_SIZE rather than NBPG. 2003-04-02 03:27:35 +00:00
hpeyerl 295e297794 de-slob-ify. (I'm a slob) 2003-04-02 02:18:52 +00:00
hpeyerl badb1c52ec OHCI front-end driver for Alchemy cpu's. We now have USB Host support. 
Tested on PB1500 and DB1500 boards.
 2003-04-01 17:36:45 +00:00
hpeyerl deece0b31e s/ohci.c/ohci_aubus.c/ 2003-04-01 17:31:50 +00:00
hpeyerl 29422429f6 add defines for Alchemy clock and frequency control registers. 2003-04-01 17:30:09 +00:00
hpeyerl 56f13f6fa9 allocate an aubus dma tag. 2003-04-01 17:29:11 +00:00
hpeyerl 9cda767630 support active low, level triggered interrupts, needed for ohci front end. 2003-04-01 17:28:24 +00:00
he fd386b5a4d Initialize new members (cn_halt and cn_flush) in consdev to NULL to 
allow this to compile again.
 2003-03-28 07:10:35 +00:00
simonb d38e1fa853 Use "rxintr" for the name of the receive interrupts evcnt instead 
of "txintr".  Much less confusing that way...
 2003-03-27 01:21:52 +00:00
simonb 0a30e5fb17 Fix a grammatical nit. 2003-03-22 14:26:41 +00:00
simonb 3c7ff59b5b Sprinkle some "volatile"; fixes problems with the {read,write}_{1,2} 
functions big-endian Au1xxx CPUs.
 2003-03-13 03:04:13 +00:00
he 0f55132c91 Initialize the two new members of "struct console" to NULL so that 
this file compiles again.
 2003-03-08 09:42:56 +00:00
rafal 67cca2386c Protect uses of MIPS_R5000 with #ifndef ENABLE_MIPS_R3NKK in new code just 
as the old code does.
 2003-03-08 05:18:25 +00:00
rafal 33fcc94c6f Add support for R5k secondary caches, from code Chris Sekiya sent me a long 
time ago, with small tweaks by me.  Since the R5k doesn't do VCE, the pmap
still needs to be whacked for R5kSC CPUs to work correctly, but this is a
start.
 2003-03-08 04:43:24 +00:00
tshiozak 31e2cbf0b5 add some ISO C 1995 I18N functions and types: 
btowc, wctrans, towctrans, wcscoll, wcsxfrm, wctype_t and wctrans_t.
 2003-03-02 22:18:11 +00:00
simonb 7a3efea0bf Make whitespace in multi-way loops line up a bit nicer. 2003-02-17 12:32:13 +00:00
simonb 8883b06039 No need to protect headers with #ifdef _KERNEL if they're never installed 
in /usr/include.
 2003-02-17 11:35:01 +00:00
cgd bc735179e8 use COP0_HAZARD_FPUENABLE in a couple more places when turning on FP: 
In start (noticed after looking for more COP_1_BIT uses, and note
that there are extra nops here but really they don't hurt), and in
MachFPTrap (noticed by ... running regress!).
 2003-02-08 00:50:33 +00:00
cgd 8a6b8c3b72 Update to consistently use Broadcom GPL-compatible license on all SiByte code. 2003-02-07 17:38:48 +00:00
cgd 045575c57d add BCM112x A2 definition 2003-02-07 17:35:05 +00:00
nakayama e3e4805068 Replace machine/rnd.h with more appropriate name to share it 
with cycle counter based microtime in kern/kern_microtime.c.
 2003-02-05 13:57:50 +00:00
kent cd7d9faeaf Introduce BUS_DMA_NOCACHE, and bus_dmamem_map() of i386 supports it. 2003-01-28 01:07:51 +00:00
simonb d77e3b36e0 Assign to pcb->pcb_context[] in the same order in cpu_lwp_fork() and 
cpu_setfunc().
 2003-01-22 13:55:09 +00:00
rafal c406903ac2 LWP'ify the svr4_mcontext stuff. 2003-01-22 04:32:17 +00:00
simonb 76cc21a34c Fix a tyop and some white-space nits. 2003-01-21 04:26:01 +00:00
thorpej 706b88727b Fix typo in sigcontext conversion macros. From Christopher SEKIYA. 2003-01-20 16:28:13 +00:00
tsutsui aa4186745b Add '#define' for _MCONTEXT_TO_SIGCONTEXT(). 2003-01-18 13:03:17 +00:00
thorpej a50e3bc1cb Merge the nathanw_sa branch. 2003-01-17 22:58:53 +00:00
simonb b2e8253950 Zero out the TX buffer when padding packet to ETHER_MIN_LEN-ETHER_CRC_LEN. 2003-01-17 12:40:20 +00:00
simonb c018fbe68d Tidy up event counter increments a little. 2003-01-16 01:14:17 +00:00
simonb c69f520bc8 Removed unused register map; this info is now passed in with the attach 
args.
 2003-01-16 01:05:39 +00:00
rafal 0cc0813590 Add the MIPS3_CONFIG_SE (name taken from Rm52xx manual) bit, which is the 
external cache enable bit -- this allows software to enable or disable the
(external) L2 cache on the R5k and Rm527x and the (external) L3 cache on
the Rm7k.  If the (external) cache is disabled, treat it as if there were
no cache for the purposes of the cache setup code.

Also, update sgimips code to use the new name.
 2003-01-10 03:22:48 +00:00
wiz 1035faff1d writable, not writeable. 2003-01-06 20:30:28 +00:00
thorpej dbb0f0ebed Use aprint_normal() for cfprint routines. 2003-01-01 01:47:30 +00:00
manu 4a06119a9d Pass the system call table to trace_enter() and ktrsys() so that it is 
possible to use alternate system call tables. This is usefull for
displaying correctly the arguments in Mach binaries traces.

If NULL is given, then the regular systam call table for the process is used.
 2002-12-21 16:23:56 +00:00
simonb 5b6caeca74 Mark the Au1x00 CPUs as having a fully coherent data cache that doesn't 
require flushing (even in the instruction cache handlers).  This gives
about a 4% improvement in a "make depend" benchmark.

Mark the SB-1 CPUs as having a fully coherent data cache that only
require flushing in the instruction cache handlers.  This gives about
a 5% improvement in a "make depend" benchmark.
 2002-12-17 12:07:50 +00:00
simonb 2c1a832f25 Add support for caches where the data cache is fully coherent, and 
either requires flushing either only when the I cache ops are used
or not at all.  Currently only used by MIPS32/MIPS64 cache code.
 2002-12-17 12:04:29 +00:00
thorpej e8cc3884de Rename __LDPGSZ to AOUT_LDPGSZ, to accurately reflect what it is. 2002-12-10 17:14:02 +00:00
thorpej 78ea2dd367 Use __LDPGSZ (which must be == USRTEXT) as the text address for a.out 
executables, and eliminate the USRTEXT constant, which was only used
by the a.out exec code.
 2002-12-10 05:14:24 +00:00
simonb 6a5e492b57 Remove the explicit `makeoptions MACHINE_ARCH="mipse{b,l}"' for kernel 
builds and use the endianness of the toolchain being used to determine
the endianness of the kernel.
 2002-12-09 22:54:09 +00:00
simonb 699bf96665 Drop the _KERNEL test; these functions are needed for SMP and other ports 
don't bother with a _KERNEL check.
 2002-12-05 02:56:51 +00:00
tsutsui d03ac2a783 Fix botch in previous. This is pcb.h, not reg.h. 2002-11-30 22:50:01 +00:00