pgoyette
67915f131f
One more typo.
...
Message to self: when making multi-architecture changes, build on more
than one arch.
2015-05-04 07:08:10 +00:00
msaitoh
215bd2a43d
Set ICH9 and ICH10's PBA size to 14K if the RX buffer size is
...
more than 4096. Almost the Same as other OSes
2015-05-04 06:51:08 +00:00
msaitoh
e3ceee8fd3
Remove WMREG_TQSA_LO and WMREG_TQSA_HIGH. Those registers
...
are not described in documents and other OS's drivers don't
access it.
(I have no the first chip(82542)'s document. Those registers
might be described in the document).
2015-05-04 06:44:13 +00:00
pgoyette
1921a9a8e3
Update mark-up
2015-05-04 06:14:47 +00:00
ryoon
f45869d2bd
Add missing .Sh SYNOPSIS
2015-05-04 05:30:48 +00:00
pgoyette
b20ab9736b
Remove extraneous blank line.
2015-05-04 03:53:41 +00:00
pgoyette
6722659ea8
Update the min and max interval values for the watchdog. The previous
...
numbers were correct, but the units for those numbers was ticks, not
seconds! (One tco watchdog tick is approximately 0.6 seconds.)
2015-05-04 03:46:28 +00:00
pgoyette
392712d661
Add new tco(4) man page to sets list.
2015-05-04 02:43:45 +00:00
pgoyette
ed66b501e0
Add new man page for tco(4), and update ichlpcib(4) man page.
2015-05-04 02:43:18 +00:00
jmcneill
10be22f9da
Remove __HAVE_MM_MD_DIRECT_MAPPED_PHYS and re-enable 2GB support, fixed
...
by arm32_kvminit.c r1.33
2015-05-04 00:59:29 +00:00
matt
9ff8857237
Deal with 4GB overflow in arm32_kvminit.c
2015-05-04 00:55:30 +00:00
matt
78ddb4758e
Deal with 2GB of ram or memory ending at or above 4GB.
2015-05-04 00:44:12 +00:00
matt
4287fca664
Fix 4GB wraparound math.
2015-05-04 00:41:42 +00:00
matt
5617d6aa97
If not using LPAE, if memory ends at 4GB ignore the last page so physical_end
...
doesn't wrap to 0.
2015-05-04 00:12:56 +00:00
pgoyette
a53699f70e
Teach a couple of i2cbus controllers how to rescan. This enables
...
{,un}loading and {at,de}taching of the iic(4) driver/module at a
later time. Tested piixpm on QEMU, and ichsmb on my live server.
2015-05-03 22:51:11 +00:00
jmcneill
6e27dfa8cf
since we dont support SDR104 yet, dont try to optimize it; instead, optimize for HS mode, which brings us up from 34 MHz to 45.333 MHz
2015-05-03 22:40:02 +00:00
jmcneill
c82d0cfd23
print some useful information at attach time
2015-05-03 22:37:27 +00:00
pgoyette
572ab4e2b8
Put the '/' back, but put it in the correct location!
2015-05-03 21:59:23 +00:00
jmcneill
5e96a9e7b1
disable MULTIPROCESSOR for now
2015-05-03 18:49:28 +00:00
jmcneill
ec484ab4fe
UART clock source is PLLP. Set com type to COM_TYPE_TEGRA.
2015-05-03 17:24:45 +00:00
jmcneill
ecb2b6ae4b
add COM_TYPE_TEGRA
2015-05-03 17:22:54 +00:00
jmcneill
bcce07f3b2
add pllc and uart rate funcs
2015-05-03 16:40:12 +00:00
matt
40d5a9d580
On secondary cores, invalidate the caches to make them clean.
2015-05-03 16:18:51 +00:00
martin
2d0cfa998a
PR 49870: pass the xsrc path to postinstall
2015-05-03 15:13:13 +00:00
joerg
432881ad82
Make sure callout is halted, not just stopped, before freeing memory.
2015-05-03 15:07:12 +00:00
hsuenaga
4e3bd6105a
add new ethernet driver mvxpe for recent MARVELL's SoC after ARMADA/XP.
...
this driver supports 'counter mode', and is disabled by default.
ARMADA SoC family has new ethernet controller acceleration mode called
'enhanced mode' or 'counter mode.' it seems that backward compatibility mode
used by if_mvgbe is still working, but the specification of the old mode
is completely disappeared from SoC's reference manual.
I tested the driver using MIRABOX(ARMADA/370).
2015-05-03 14:38:09 +00:00
wiz
593de75e05
Sort SEE ALSO.
2015-05-03 12:29:28 +00:00
wiz
a4569887ef
Sort ERRORS and SEE ALSO.
2015-05-03 12:27:32 +00:00
jmcneill
64afd1ea16
when setting sdmmc divisor, do a full reset / enable sequence
2015-05-03 11:47:15 +00:00
jmcneill
10c0159579
set SDHC_FLAG_SINGLE_POWER_WRITE
2015-05-03 11:46:44 +00:00
jmcneill
e974ccfaa2
Add SDHC_FLAG_SINGLE_POWER_WRITE flag, that tells the driver to update
...
the SDHC_POWER_CTL register with a single write rather than in multiple
steps. Required for Tegra K1 SDHC.
2015-05-03 11:46:25 +00:00
justin
f5df4fc799
Rename delay variable as it shadows a global on arm.
2015-05-03 10:44:04 +00:00
pgoyette
5929e90778
Fix typo, fix the build-break. One '/' is enough in path names.
2015-05-03 07:30:52 +00:00
msaitoh
560d01237b
regen.
2015-05-03 06:29:48 +00:00
hsuenaga
3cf6633124
write back unaligned boundary of L2 cache even if invalidate operation
...
is requested.
2015-05-03 06:29:31 +00:00
msaitoh
38b43c2941
Add some NVIDIA devices.
2015-05-03 06:29:21 +00:00
rtr
5f2c7f7738
flip (NULL == addr) to (addr == NULL) use in conditional from previous
...
commit.
2015-05-03 04:18:45 +00:00
pgoyette
6fb6cabb23
Include the new tco module on i386 and amd64 builds
2015-05-03 02:55:04 +00:00
pgoyette
90df75aa93
Build the tco watchdog module
2015-05-03 02:54:07 +00:00
pgoyette
5b9fcd9abb
Update to include the tco driver (it was previously included as part of
...
ichlpcib).
2015-05-03 02:52:50 +00:00
pgoyette
ed77961ac5
Separate the watchdog code from the pcib code, and make the watchdog
...
a loadable module.
2015-05-03 02:50:59 +00:00
jmcneill
e114a7d535
coherent dma tag doesnt quite work
2015-05-03 01:26:44 +00:00
jmcneill
e1b20f2837
Add Tegra K1 PCIE support.
2015-05-03 01:07:44 +00:00
matt
99f92b6303
Deal with 64-bit BARs
2015-05-03 00:04:06 +00:00
rtr
f6bef303da
compare mbuf * pointer to NULL instead of 0
2015-05-02 23:46:04 +00:00
christos
a6b82aa2c6
grow it a bit.
2015-05-02 23:21:40 +00:00
rtr
c027610558
remove unnecessary check that nam != NULL before deref in soconnect()
...
(added in previous commit).
sockargs copyin() makes sure we don't get NULL here
2015-05-02 21:15:33 +00:00
joerg
5cad40c933
Fix !ARP build.
2015-05-02 20:22:12 +00:00
rtr
487c8ce86e
make soconnect() fail with EAFNOSUPPORT if the domain of the socket does
...
not match family received in the sockaddr.
* connect() now fails as documented in connect(2).
* atf test t_connect:connect_foreign_family now passes.
2015-05-02 20:10:26 +00:00
matt
f1588c096e
For mips64, build kmodules using N64 ABI
2015-05-02 18:18:13 +00:00
