add new ethernet driver mvxpe for recent MARVELL's SoC after ARMADA/XP.
this driver supports 'counter mode', and is disabled by default. ARMADA SoC family has new ethernet controller acceleration mode called 'enhanced mode' or 'counter mode.' it seems that backward compatibility mode used by if_mvgbe is still working, but the specification of the old mode is completely disappeared from SoC's reference manual. I tested the driver using MIRABOX(ARMADA/370).
This commit is contained in:
hsuenaga
parent
593de75e05
commit
4e3bd6105a
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@ -1,4 +1,4 @@
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# $NetBSD: files.marvell,v 1.13 2014/03/18 07:25:57 matt Exp $
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# $NetBSD: files.marvell,v 1.14 2015/05/03 14:38:09 hsuenaga Exp $
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#
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# Configuration info for Marvell System on Chip support
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#
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@ -57,6 +57,12 @@ attach mvsata at mvsoc with mvsata_mbus
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# Gigabit Ethernet Controller Interface
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attach mvgbec at mvsoc with mvgbec_mbus
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# ARMADA XP Gigabit Ethernet Controller Interface
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define mvxpe { [port = -1 ], [irq = -1] }
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device mvxpe: ether, ifnet, arp, mii
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attach mvxpe at mvsoc with mvxpe_mbus
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file dev/marvell/if_mvxpe.c mvxpe needs-flag
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# USB 2.0 Interface
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attach ehci at mvsoc with mvusb_mbus
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@ -1,4 +1,4 @@
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/* $NetBSD: mvsoc.c,v 1.18 2014/03/15 11:48:37 kiyohara Exp $ */
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/* $NetBSD: mvsoc.c,v 1.19 2015/05/03 14:38:09 hsuenaga Exp $ */
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/*
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* Copyright (c) 2007, 2008, 2013, 2014 KIYOHARA Takashi
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* All rights reserved.
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@ -26,10 +26,11 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: mvsoc.c,v 1.18 2014/03/15 11:48:37 kiyohara Exp $");
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__KERNEL_RCSID(0, "$NetBSD: mvsoc.c,v 1.19 2015/05/03 14:38:09 hsuenaga Exp $");
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#include "opt_cputypes.h"
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#include "opt_mvsoc.h"
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#include "mvxpe.h"
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#include <sys/param.h>
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#include <sys/bus.h>
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@ -675,9 +676,14 @@ static const struct mvsoc_periph {
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{ ARMADAXP(MV78130), "mvsata", 0, ARMADAXP_SATAHC_BASE,ARMADAXP_IRQ_SATA0 },
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{ ARMADAXP(MV78130), "mvspi", 0, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI },
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{ ARMADAXP(MV78130), "mvsdio", 0, ARMADAXP_SDIO_BASE,ARMADAXP_IRQ_SDIO },
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{ ARMADAXP(MV78130), "mvgbec", 0, ARMADAXP_GBE0_BASE,IRQ_DEFAULT },
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{ ARMADAXP(MV78130), "mvxpe", 0, ARMADAXP_GBE0_BASE,ARMADAXP_IRQ_GBE0_TH_RXTX },
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#if NMVXPE > 0
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{ ARMADAXP(MV78130), "mvxpe", 1, ARMADAXP_GBE1_BASE,ARMADAXP_IRQ_GBE1_TH_RXTX },
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{ ARMADAXP(MV78130), "mvxpe", 2, ARMADAXP_GBE2_BASE,ARMADAXP_IRQ_GBE2_TH_RXTX },
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#else
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{ ARMADAXP(MV78130), "mvgbec", 1, ARMADAXP_GBE1_BASE,IRQ_DEFAULT },
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{ ARMADAXP(MV78130), "mvgbec", 2, ARMADAXP_GBE2_BASE,IRQ_DEFAULT },
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#endif
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{ ARMADAXP(MV78130), "mvcesa", 0, ARMADAXP_CESA0_BASE,ARMADAXP_IRQ_CESA0 },
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{ ARMADAXP(MV78130), "mvcesa", 1, ARMADAXP_CESA1_BASE,ARMADAXP_IRQ_CESA1 },
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@ -702,10 +708,17 @@ static const struct mvsoc_periph {
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{ ARMADAXP(MV78160), "mvsata", 0, ARMADAXP_SATAHC_BASE,ARMADAXP_IRQ_SATA0 },
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{ ARMADAXP(MV78160), "mvspi", 0, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI },
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{ ARMADAXP(MV78160), "mvsdio", 0, ARMADAXP_SDIO_BASE,ARMADAXP_IRQ_SDIO },
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#if NMVXPE > 0
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{ ARMADAXP(MV78160), "mvxpe", 0, ARMADAXP_GBE0_BASE,ARMADAXP_IRQ_GBE0_TH_RXTX },
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{ ARMADAXP(MV78160), "mvxpe", 1, ARMADAXP_GBE1_BASE,ARMADAXP_IRQ_GBE1_TH_RXTX },
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{ ARMADAXP(MV78160), "mvxpe", 2, ARMADAXP_GBE2_BASE,ARMADAXP_IRQ_GBE2_TH_RXTX },
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{ ARMADAXP(MV78160), "mvxpe", 3, ARMADAXP_GBE3_BASE,ARMADAXP_IRQ_GBE3_TH_RXTX },
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#else
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{ ARMADAXP(MV78160), "mvgbec", 0, ARMADAXP_GBE0_BASE,IRQ_DEFAULT },
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{ ARMADAXP(MV78160), "mvgbec", 1, ARMADAXP_GBE1_BASE,IRQ_DEFAULT },
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{ ARMADAXP(MV78160), "mvgbec", 2, ARMADAXP_GBE2_BASE,IRQ_DEFAULT },
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{ ARMADAXP(MV78160), "mvgbec", 3, ARMADAXP_GBE3_BASE,IRQ_DEFAULT },
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#endif
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{ ARMADAXP(MV78160), "mvcesa", 0, ARMADAXP_CESA0_BASE,ARMADAXP_IRQ_CESA0 },
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{ ARMADAXP(MV78160), "mvcesa", 1, ARMADAXP_CESA1_BASE,ARMADAXP_IRQ_CESA1 },
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@ -730,9 +743,15 @@ static const struct mvsoc_periph {
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{ ARMADAXP(MV78230), "mvsata", 0, ARMADAXP_SATAHC_BASE,ARMADAXP_IRQ_SATA0 },
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{ ARMADAXP(MV78230), "mvspi", 0, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI },
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{ ARMADAXP(MV78230), "mvsdio", 0, ARMADAXP_SDIO_BASE,ARMADAXP_IRQ_SDIO },
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#if NMVXPE > 0
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{ ARMADAXP(MV78230), "mvxpe", 0, ARMADAXP_GBE0_BASE,ARMADAXP_IRQ_GBE0_TH_RXTX },
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{ ARMADAXP(MV78230), "mvxpe", 1, ARMADAXP_GBE1_BASE,ARMADAXP_IRQ_GBE1_TH_RXTX },
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{ ARMADAXP(MV78230), "mvxpe", 2, ARMADAXP_GBE2_BASE,ARMADAXP_IRQ_GBE2_TH_RXTX },
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#else
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{ ARMADAXP(MV78230), "mvgbec", 0, ARMADAXP_GBE0_BASE,IRQ_DEFAULT },
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{ ARMADAXP(MV78230), "mvgbec", 1, ARMADAXP_GBE1_BASE,IRQ_DEFAULT },
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{ ARMADAXP(MV78230), "mvgbec", 2, ARMADAXP_GBE2_BASE,IRQ_DEFAULT },
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#endif
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{ ARMADAXP(MV78230), "mvcesa", 0, ARMADAXP_CESA0_BASE,ARMADAXP_IRQ_CESA0 },
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{ ARMADAXP(MV78230), "mvcesa", 1, ARMADAXP_CESA1_BASE,ARMADAXP_IRQ_CESA1 },
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@ -757,10 +776,17 @@ static const struct mvsoc_periph {
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{ ARMADAXP(MV78260), "mvsata", 0, ARMADAXP_SATAHC_BASE,ARMADAXP_IRQ_SATA0 },
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{ ARMADAXP(MV78260), "mvspi", 0, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI },
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{ ARMADAXP(MV78260), "mvsdio", 0, ARMADAXP_SDIO_BASE,ARMADAXP_IRQ_SDIO },
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#if NMVXPE > 0
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{ ARMADAXP(MV78260), "mvxpe", 0, ARMADAXP_GBE0_BASE,ARMADAXP_IRQ_GBE0_TH_RXTX },
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{ ARMADAXP(MV78260), "mvxpe", 1, ARMADAXP_GBE1_BASE,ARMADAXP_IRQ_GBE1_TH_RXTX },
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{ ARMADAXP(MV78260), "mvxpe", 2, ARMADAXP_GBE2_BASE,ARMADAXP_IRQ_GBE2_TH_RXTX },
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{ ARMADAXP(MV78260), "mvxpe", 3, ARMADAXP_GBE3_BASE,ARMADAXP_IRQ_GBE3_TH_RXTX },
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#else
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{ ARMADAXP(MV78260), "mvgbec", 0, ARMADAXP_GBE0_BASE,IRQ_DEFAULT },
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{ ARMADAXP(MV78260), "mvgbec", 1, ARMADAXP_GBE1_BASE,IRQ_DEFAULT },
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{ ARMADAXP(MV78260), "mvgbec", 2, ARMADAXP_GBE2_BASE,IRQ_DEFAULT },
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{ ARMADAXP(MV78260), "mvgbec", 3, ARMADAXP_GBE3_BASE,IRQ_DEFAULT },
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#endif
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{ ARMADAXP(MV78260), "mvcesa", 0, ARMADAXP_CESA0_BASE,ARMADAXP_IRQ_CESA0 },
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{ ARMADAXP(MV78260), "mvcesa", 1, ARMADAXP_CESA1_BASE,ARMADAXP_IRQ_CESA1 },
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@ -786,10 +812,17 @@ static const struct mvsoc_periph {
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{ ARMADAXP(MV78460), "mvsata", 0, ARMADAXP_SATAHC_BASE,ARMADAXP_IRQ_SATA0 },
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{ ARMADAXP(MV78460), "mvspi", 0, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI },
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{ ARMADAXP(MV78460), "mvsdio", 0, ARMADAXP_SDIO_BASE,ARMADAXP_IRQ_SDIO },
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#if NMVXPE > 0
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{ ARMADAXP(MV78460), "mvxpe", 0, ARMADAXP_GBE0_BASE,ARMADAXP_IRQ_GBE0_TH_RXTX },
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{ ARMADAXP(MV78460), "mvxpe", 1, ARMADAXP_GBE1_BASE,ARMADAXP_IRQ_GBE1_TH_RXTX },
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{ ARMADAXP(MV78460), "mvxpe", 2, ARMADAXP_GBE2_BASE,ARMADAXP_IRQ_GBE2_TH_RXTX },
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{ ARMADAXP(MV78460), "mvxpe", 3, ARMADAXP_GBE3_BASE,ARMADAXP_IRQ_GBE3_TH_RXTX },
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#else
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{ ARMADAXP(MV78460), "mvgbec", 0, ARMADAXP_GBE0_BASE,IRQ_DEFAULT },
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{ ARMADAXP(MV78460), "mvgbec", 1, ARMADAXP_GBE1_BASE,IRQ_DEFAULT },
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{ ARMADAXP(MV78460), "mvgbec", 2, ARMADAXP_GBE2_BASE,IRQ_DEFAULT },
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{ ARMADAXP(MV78460), "mvgbec", 3, ARMADAXP_GBE3_BASE,IRQ_DEFAULT },
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#endif
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{ ARMADAXP(MV78460), "mvcesa", 0, ARMADAXP_CESA0_BASE,ARMADAXP_IRQ_CESA0 },
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{ ARMADAXP(MV78460), "mvcesa", 1, ARMADAXP_CESA1_BASE,ARMADAXP_IRQ_CESA1 },
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@ -808,8 +841,13 @@ static const struct mvsoc_periph {
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{ ARMADA370(MV6710), "mvspi", 0, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI },
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{ ARMADA370(MV6710), "mvspi", 1, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI },
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{ ARMADA370(MV6710), "mvsdio", 0, ARMADAXP_SDIO_BASE,ARMADAXP_IRQ_SDIO },
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#if NMVXPE > 0
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{ ARMADA370(MV6710), "mvxpe", 0, ARMADAXP_GBE0_BASE,ARMADAXP_IRQ_GBE0_TH_RXTX },
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{ ARMADA370(MV6710), "mvxpe", 1, ARMADAXP_GBE1_BASE,ARMADAXP_IRQ_GBE1_TH_RXTX },
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#else
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{ ARMADA370(MV6710), "mvgbec", 0, ARMADAXP_GBE0_BASE,IRQ_DEFAULT },
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{ ARMADA370(MV6710), "mvgbec", 1, ARMADAXP_GBE1_BASE,IRQ_DEFAULT },
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#endif
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{ ARMADA370(MV6710), "mvcesa", 0, ARMADAXP_CESA0_BASE,ARMADAXP_IRQ_CESA0 },
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#endif
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};
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@ -1,4 +1,4 @@
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/* $NetBSD: armadaxp_machdep.c,v 1.10 2015/04/15 10:30:42 hsuenaga Exp $ */
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/* $NetBSD: armadaxp_machdep.c,v 1.11 2015/05/03 14:38:10 hsuenaga Exp $ */
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/*******************************************************************************
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Copyright (C) Marvell International Ltd. and its affiliates
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@ -37,7 +37,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: armadaxp_machdep.c,v 1.10 2015/04/15 10:30:42 hsuenaga Exp $");
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__KERNEL_RCSID(0, "$NetBSD: armadaxp_machdep.c,v 1.11 2015/05/03 14:38:10 hsuenaga Exp $");
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#include "opt_machdep.h"
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#include "opt_mvsoc.h"
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@ -66,6 +66,7 @@ __KERNEL_RCSID(0, "$NetBSD: armadaxp_machdep.c,v 1.10 2015/04/15 10:30:42 hsuena
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#include <dev/cons.h>
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#include <dev/md.h>
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#include <dev/marvell/marvellreg.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include <machine/pci_machdep.h>
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@ -620,6 +621,31 @@ axp_device_register(device_t dev, void *aux)
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char optname[9];
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int unit = device_unit(dev);
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if (unit > 9)
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return;
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switch (unit) {
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case 0:
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strlcpy(optname, "ethaddr", sizeof(optname));
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break;
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default:
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/* eth1addr ... eth9addr */
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snprintf(optname, sizeof(optname),
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"eth%daddr", unit);
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break;
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}
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if (get_bootconf_option(boot_args, optname,
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BOOTOPT_TYPE_MACADDR, enaddr)) {
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prop_data_t pd =
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prop_data_create_data(enaddr, sizeof(enaddr));
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prop_dictionary_set(dict, "mac-address", pd);
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}
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}
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if (device_is_a(dev, "mvxpe")) {
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uint8_t enaddr[ETHER_ADDR_LEN];
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char optname[9];
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int unit = device_unit(dev);
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if (unit > 9)
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return;
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switch (unit) {
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@ -1,4 +1,4 @@
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/* $NetBSD: marvellvar.h,v 1.3 2014/03/18 07:30:09 matt Exp $ */
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/* $NetBSD: marvellvar.h,v 1.4 2015/05/03 14:38:10 hsuenaga Exp $ */
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/*
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* Copyright (c) 2007 KIYOHARA Takashi
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* All rights reserved.
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@ -26,6 +26,9 @@
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*/
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#ifndef _EVBARM_MARVELLVAR_H_
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#define _EVBARM_MARVELLVAR_H_
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#ifndef _LOCORE
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#include <machine/bus_defs.h>
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#endif
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/*
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* Logical mapping for onboard/integrated peripherals
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,890 @@
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/* $NetBSD: if_mvxpereg.h,v 1.1 2015/05/03 14:38:10 hsuenaga Exp $ */
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/*
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* Copyright (c) 2015 Internet Initiative Japan Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _IF_MVXPEREG_H_
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#define _IF_MVXPEREG_H_
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#if BYTE_ORDER == BIG_ENDIAN
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#error "BIG ENDIAN not supported"
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#endif
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#define MVXPE_SIZE 0x4000
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#define MVXPE_NWINDOW 6
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#define MVXPE_NREMAP 4
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#define MVXPE_QUEUE_SIZE 8
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#define MVXPE_QUEUE(n) (1 << (n))
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#define MVXPE_QUEUE_ALL 0xff
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/*
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* Ethernet Unit Registers
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* GbE0 BASE 0x00007.0000 SIZE 0x4000
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* GbE1 BASE 0x00007.4000 SIZE 0x4000
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*
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* TBD: reasonable bus space submapping....
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*/
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/* Address Decoder Registers */
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#define MVXPE_BASEADDR(n) (0x2200 + ((n) << 3)) /* Base Address */
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#define MVXPE_S(n) (0x2204 + ((n) << 3)) /* Size */
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#define MVXPE_HA(n) (0x2280 + ((n) << 2)) /* High Address Remap */
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#define MVXPE_BARE 0x2290 /* Base Address Enable */
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#define MVXPE_EPAP 0x2294 /* Ethernet Port Access Protect */
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/* Global Miscellaneous Registers */
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#define MVXPE_PHYADDR 0x2000
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#define MVXPE_SMI 0x2004
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#define MVXPE_EUDA 0x2008 /* Ethernet Unit Default Address */
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#define MVXPE_EUDID 0x200c /* Ethernet Unit Default ID */
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#define MVXPE_EUIC 0x2080 /* Ethernet Unit Interrupt Cause */
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#define MVXPE_EUIM 0x2084 /* Ethernet Unit Interrupt Mask */
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#define MVXPE_EUEA 0x2094 /* Ethernet Unit Error Address */
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#define MVXPE_EUIAE 0x2098 /* Ethernet Unit Internal Addr Error */
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#define MVXPE_EUC 0x20b0 /* Ethernet Unit Control */
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/* Miscellaneous Registers */
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#define MVXPE_SDC 0x241c /* SDMA Configuration */
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/* Networking Controller Miscellaneous Registers */
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#define MVXPE_PACC 0x2500 /* Port Acceleration Mode */
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#define MVXPE_PV 0x25bc /* Port Version */
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/* Rx DMA Hardware Parser Registers */
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#define MVXPE_EVLANE 0x2410 /* VLAN EtherType */
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#define MVXPE_MACAL 0x2414 /* MAC Address Low */
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#define MVXPE_MACAH 0x2418 /* MAC Address High */
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#define MVXPE_NDSCP 7
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#define MVXPE_DSCP(n) (0x2420 + ((n) << 2))
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#define MVXPE_VPT2P 0x2440 /* VLAN Priority Tag to Priority */
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#define MVXPE_ETP 0x24bc /* Ethernet Type Priority */
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#define MVXPE_NDFSMT 64
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#define MVXPE_DFSMT(n) (0x3400 + ((n) << 2))
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/* Destination Address Filter Special Multicast Table */
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#define MVXPE_NDFOMT 64
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#define MVXPE_DFOMT(n) (0x3500 + ((n) << 2))
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/* Destination Address Filter Other Multicast Table */
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#define MVXPE_NDFUT 4
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#define MVXPE_DFUT(n) (0x3600 + ((n) << 2))
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/* Destination Address Filter Unicast Table */
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/* Rx DMA Miscellaneous Registers */
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#define MVXPE_PMFS 0x247c /* Port Rx Minimal Frame Size */
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||||
#define MVXPE_PDFC 0x2484 /* Port Rx Discard Frame Counter */
|
||||
#define MVXPE_POFC 0x2488 /* Port Overrun Frame Counter */
|
||||
#define MVXPE_RQC 0x2680 /* Receive Queue Command */
|
||||
|
||||
/* Rx DMA Networking Controller Miscellaneous Registers */
|
||||
#define MVXPE_PRXC(q) (0x1400 + ((q) << 2)) /*Port RX queues Config*/
|
||||
#define MVXPE_PRXSNP(q) (0x1420 + ((q) << 2)) /* Port RX queues Snoop */
|
||||
#define MVXPE_PRXDQA(q) (0x1480 + ((q) << 2)) /*P RXqueues desc Q Addr*/
|
||||
#define MVXPE_PRXDQS(q) (0x14a0 + ((q) << 2)) /*P RXqueues desc Q Size*/
|
||||
#define MVXPE_PRXDQTH(q) (0x14c0 + ((q) << 2)) /*P RXqueues desc Q Thrs*/
|
||||
#define MVXPE_PRXS(q) (0x14e0 + ((q) << 2)) /*Port RX queues Status */
|
||||
#define MVXPE_PRXSU(q) (0x1500 + ((q) << 2)) /*P RXqueues Stat Update*/
|
||||
#define MVXPE_PRXDI(q) (0x1520 + ((q) << 2)) /*P RXqueues Stat Update*/
|
||||
#define MVXPE_PRXINIT 0x1cc0 /* Port RX Initialization */
|
||||
|
||||
/* Rx DMA Wake on LAN Registers 0x3690 - 0x36b8 */
|
||||
|
||||
/* Tx DMA Miscellaneous Registers */
|
||||
#define MVXPE_TQC 0x2448 /* Transmit Queue Command */
|
||||
#define MVXPE_PXTFTT 0x2478 /* Port Tx FIFO Threshold */
|
||||
#define MVXPE_TXBADFCS 0x3cc0 /*Tx Bad FCS Transmitted Pckts Counter*/
|
||||
#define MVXPE_TXDROPPED 0x3cc4 /* Tx Dropped Packets Counter */
|
||||
|
||||
/* Tx DMA Networking Controller Miscellaneous Registers */
|
||||
#define MVXPE_PTXDQA(q) (0x3c00 + ((q) << 2)) /*P TXqueues desc Q Addr*/
|
||||
#define MVXPE_PTXDQS(q) (0x3c20 + ((q) << 2)) /*P TXqueues desc Q Size*/
|
||||
#define MVXPE_PTXS(q) (0x3c40 + ((q) << 2)) /* Port TX queues Status*/
|
||||
#define MVXPE_PTXSU(q) (0x3c60 + ((q) << 2)) /*P TXqueues Stat Update*/
|
||||
#define MVXPE_PTXDI(q) (0x3c80 + ((q) << 2)) /* P TXqueues Desc Index*/
|
||||
#define MVXPE_TXTBC(q) (0x3ca0 + ((q) << 2)) /* TX Trans-ed Buf Count*/
|
||||
#define MVXPE_PTXINIT 0x3cf0 /* Port TX Initialization */
|
||||
|
||||
/* Tx DMA Packet Modification Registers */
|
||||
#define MVXPE_NMH 15
|
||||
#define MVXPE_TXMH(n) (0x3d44 + ((n) << 2))
|
||||
#define MVXPE_TXMTU 0x3d88
|
||||
|
||||
/* Tx DMA Queue Arbiter Registers (Version 1) */
|
||||
#define MVXPE_TQFPC_V1 0x24dc /* Transmit Queue Fixed Priority Cfg */
|
||||
#define MVXPE_TQTBC_V1 0x24e0 /* Transmit Queue Token-Bucket Cfg */
|
||||
#define MVXPE_MTU_V1 0x24e8 /* MTU */
|
||||
#define MVXPE_PMTBS_V1 0x24ec /* Port Max Token-Bucket Size */
|
||||
#define MVXPE_TQTBCOUNT_V1(q) (0x2700 + ((q) << 4))
|
||||
/* Transmit Queue Token-Bucket Counter */
|
||||
#define MVXPE_TQTBCONFIG_V1(q) (0x2704 + ((q) << 4))
|
||||
/* Transmit Queue Token-Bucket Configuration */
|
||||
#define MVXPE_PTTBC_V1 0x2740 /* Port Transmit Backet Counter */
|
||||
|
||||
/* Tx DMA Queue Arbiter Registers (Version 3) */
|
||||
#define MVXPE_TQC1_V3 0x3e00 /* Transmit Queue Command1 */
|
||||
#define MVXPE_TQFPC_V3 0x3e04 /* Transmit Queue Fixed Priority Cfg */
|
||||
#define MVXPE_BRC_V3 0x3e08 /* Basic Refill No of Clocks */
|
||||
#define MVXPE_MTU_V3 0x3e0c /* MTU */
|
||||
#define MVXPE_PREFILL_V3 0x3e10 /* Port Backet Refill */
|
||||
#define MVXPE_PMTBS_V3 0x3e14 /* Port Max Token-Bucket Size */
|
||||
#define MVXPE_QREFILL_V3(q) (0x3e20 + ((q) << 2))
|
||||
/* Transmit Queue Refill */
|
||||
#define MVXPE_QMTBS_V3(q) (0x3e40 + ((q) << 2))
|
||||
/* Transmit Queue Max Token-Bucket Size */
|
||||
#define MVXPE_QTTBC_V3(q) (0x3e60 + ((q) << 2))
|
||||
/* Transmit Queue Token-Bucket Counter */
|
||||
#define MVXPE_TQAC_V3(q) (0x3e80 + ((q) << 2))
|
||||
/* Transmit Queue Arbiter Cfg */
|
||||
#define MVXPE_TQIPG_V3(q) (0x3ea0 + ((q) << 2))
|
||||
/* Transmit Queue IPG(valid q=2..3) */
|
||||
#define MVXPE_HITKNINLOPKT_V3 0x3eb0 /* High Token in Low Packet */
|
||||
#define MVXPE_HITKNINASYNCPKT_V3 0x3eb4 /* High Token in Async Packet */
|
||||
#define MVXPE_LOTKNINASYNCPKT_V3 0x3eb8 /* Low Token in Async Packet */
|
||||
#define MVXPE_TS_V3 0x3ebc /* Token Speed */
|
||||
|
||||
/* RX_TX DMA Registers */
|
||||
#define MVXPE_PXC 0x2400 /* Port Configuration */
|
||||
#define MVXPE_PXCX 0x2404 /* Port Configuration Extend */
|
||||
#define MVXPE_MH 0x2454 /* Marvell Header */
|
||||
|
||||
/* Serial(SMI/MII) Registers */
|
||||
#define MVXPE_PSC0 0x243c /* Port Serial Control0 */
|
||||
#define MVXPE_PS0 0x2444 /* Ethernet Port Status */
|
||||
#define MVXPE_PSERDESCFG 0x24a0 /* Serdes Configuration */
|
||||
#define MVXPE_PSERDESSTS 0x24a4 /* Serdes Status */
|
||||
#define MVXPE_PSOMSCD 0x24f4 /* One mS Clock Divider */
|
||||
#define MVXPE_PSPFCCD 0x24f8 /* Periodic Flow Control Clock Divider*/
|
||||
|
||||
/* Gigabit Ethernet MAC Serial Parameters Configuration Registers */
|
||||
#define MVXPE_PSPC 0x2c14 /* Port Serial Parameters Config */
|
||||
#define MVXPE_PSP1C 0x2c94 /* Port Serial Parameters 1 Config */
|
||||
|
||||
/* Gigabit Ethernet Auto-Negotiation Configuration Registers */
|
||||
#define MVXPE_PANC 0x2c0c /* Port Auto-Negotiation Configuration*/
|
||||
|
||||
/* Gigabit Ethernet MAC Control Registers */
|
||||
#define MVXPE_PMACC0 0x2c00 /* Port MAC Control 0 */
|
||||
#define MVXPE_PMACC1 0x2c04 /* Port MAC Control 1 */
|
||||
#define MVXPE_PMACC2 0x2c08 /* Port MAC Control 2 */
|
||||
#define MVXPE_PMACC3 0x2c48 /* Port MAC Control 3 */
|
||||
#define MVXPE_CCFCPST(p) (0x2c58 + ((p) << 2)) /*CCFC Port Speed Timerp*/
|
||||
#define MVXPE_PMACC4 0x2c90 /* Port MAC Control 4 */
|
||||
|
||||
/* Gigabit Ethernet MAC Interrupt Registers */
|
||||
#define MVXPE_PIC 0x2c20
|
||||
#define MVXPE_PIM 0x2c24
|
||||
|
||||
/* Gigabit Ethernet Low Power Idle Registers */
|
||||
#define MVXPE_LPIC0 0x2cc0 /* LowPowerIdle control 0 */
|
||||
#define MVXPE_LPIC1 0x2cc4 /* LPI control 1 */
|
||||
#define MVXPE_LPIC2 0x2cc8 /* LPI control 2 */
|
||||
#define MVXPE_LPIS 0x2ccc /* LPI status */
|
||||
#define MVXPE_LPIC 0x2cd0 /* LPI counter */
|
||||
|
||||
/* Gigabit Ethernet MAC PRBS Check Status Registers */
|
||||
#define MVXPE_PPRBSS 0x2c38 /* Port PRBS Status */
|
||||
#define MVXPE_PPRBSEC 0x2c3c /* Port PRBS Error Counter */
|
||||
|
||||
/* Gigabit Ethernet MAC Status Registers */
|
||||
#define MVXPE_PSR 0x2c10 /* Port Status Register0 */
|
||||
|
||||
/* Networking Controller Interrupt Registers */
|
||||
#define MVXPE_PRXITTH(q) (0x2580 + ((q) << 2))
|
||||
/* Port Rx Interrupt Threshold */
|
||||
#define MVXPE_PRXTXTIC 0x25a0 /*Port RX_TX Threshold Interrupt Cause*/
|
||||
#define MVXPE_PRXTXTIM 0x25a4 /*Port RX_TX Threshold Interrupt Mask */
|
||||
#define MVXPE_PRXTXIC 0x25a8 /* Port RX_TX Interrupt Cause */
|
||||
#define MVXPE_PRXTXIM 0x25ac /* Port RX_TX Interrupt Mask */
|
||||
#define MVXPE_PMIC 0x25b0 /* Port Misc Interrupt Cause */
|
||||
#define MVXPE_PMIM 0x25b4 /* Port Misc Interrupt Mask */
|
||||
#define MVXPE_PIE 0x25b8 /* Port Interrupt Enable */
|
||||
|
||||
/* Miscellaneous Interrupt Registers */
|
||||
#define MVXPE_PEUIAE 0x2494 /* Port Internal Address Error */
|
||||
|
||||
/* SGMII PHY Registers */
|
||||
#define MVXPE_PPLLC 0x2e04 /* Power and PLL Control */
|
||||
#define MVXPE_TESTC0 0x2e54 /* PHY Test Control 0 */
|
||||
#define MVXPE_TESTPRBSEC0 0x2e7c /* PHY Test PRBS Erorr Counter 0 */
|
||||
#define MVXPE_TESTPRBSEC1 0x2e80 /* PHY Test PRBS Erorr Counter 1 */
|
||||
#define MVXPE_TESTOOB0 0x2e84 /* PHY Test OOB 0 */
|
||||
#define MVXPE_DLE 0x2e8c /* Digital Loopback Enable */
|
||||
#define MVXPE_RCS 0x2f18 /* Reference Clock Select */
|
||||
#define MVXPE_COMPHYC 0x2f18 /* COMPHY Control */
|
||||
|
||||
/*
|
||||
* Ethernet MAC MIB Registers
|
||||
* GbE0 BASE 0x00007.3000
|
||||
* GbE1 BASE 0x00007.7000
|
||||
*/
|
||||
/* MAC MIB Counters 0x3000 - 0x307c */
|
||||
#define MVXPE_PORTMIB_BASE 0x3000
|
||||
#define MVXPE_PORTMIB_SIZE 0x0100
|
||||
|
||||
/* Rx */
|
||||
#define MVXPE_MIB_RX_GOOD_OCT 0x00 /* 64bit */
|
||||
#define MVXPE_MIB_RX_BAD_OCT 0x08
|
||||
#define MVXPE_MIB_RX_MAC_TRNS_ERR 0x0c
|
||||
#define MVXPE_MIB_RX_GOOD_FRAME 0x10
|
||||
#define MVXPE_MIB_RX_BAD_FRAME 0x14
|
||||
#define MVXPE_MIB_RX_BCAST_FRAME 0x18
|
||||
#define MVXPE_MIB_RX_MCAST_FRAME 0x1c
|
||||
#define MVXPE_MIB_RX_FRAME64_OCT 0x20
|
||||
#define MVXPE_MIB_RX_FRAME127_OCT 0x24
|
||||
#define MVXPE_MIB_RX_FRAME255_OCT 0x28
|
||||
#define MVXPE_MIB_RX_FRAME511_OCT 0x2c
|
||||
#define MVXPE_MIB_RX_FRAME1023_OCT 0x30
|
||||
#define MVXPE_MIB_RX_FRAMEMAX_OCT 0x34
|
||||
|
||||
/* Tx */
|
||||
#define MVXPE_MIB_TX_GOOD_OCT 0x38 /* 64bit */
|
||||
#define MVXPE_MIB_TX_GOOD_FRAME 0x40
|
||||
#define MVXPE_MIB_TX_EXCES_COL 0x44
|
||||
#define MVXPE_MIB_TX_MCAST_FRAME 0x48
|
||||
#define MVXPE_MIB_TX_BCAST_FRAME 0x4c
|
||||
#define MVXPE_MIB_TX_MAC_CTL_ERR 0x50
|
||||
|
||||
/* Flow Control */
|
||||
#define MVXPE_MIB_FC_SENT 0x54
|
||||
#define MVXPE_MIB_FC_GOOD 0x58
|
||||
#define MVXPE_MIB_FC_BAD 0x5c
|
||||
|
||||
/* Packet Processing */
|
||||
#define MVXPE_MIB_PKT_UNDERSIZE 0x60
|
||||
#define MVXPE_MIB_PKT_FRAGMENT 0x64
|
||||
#define MVXPE_MIB_PKT_OVERSIZE 0x68
|
||||
#define MVXPE_MIB_PKT_JABBER 0x6c
|
||||
|
||||
/* MAC Layer Errors */
|
||||
#define MVXPE_MIB_MAC_RX_ERR 0x70
|
||||
#define MVXPE_MIB_MAC_CRC_ERR 0x74
|
||||
#define MVXPE_MIB_MAC_COL 0x78
|
||||
#define MVXPE_MIB_MAC_LATE_COL 0x7c
|
||||
|
||||
/* END OF REGISTER NUMBERS */
|
||||
|
||||
/*
|
||||
*
|
||||
* Register Formats
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Address Decoder Registers
|
||||
*/
|
||||
/* Base Address (MVXPE_BASEADDR) */
|
||||
#define MVXPE_BASEADDR_TARGET(target) ((target) & 0xf)
|
||||
#define MVXPE_BASEADDR_ATTR(attr) (((attr) & 0xff) << 8)
|
||||
#define MVXPE_BASEADDR_BASE(base) ((base) & 0xffff0000)
|
||||
|
||||
/* Size (MVXPE_S) */
|
||||
#define MVXPE_S_SIZE(size) (((size) - 1) & 0xffff0000)
|
||||
|
||||
/* Base Address Enable (MVXPE_BARE) */
|
||||
#define MVXPE_BARE_EN_MASK ((1 << MVXPE_NWINDOW) - 1)
|
||||
#define MVXPE_BARE_EN(win) ((1 << (win)) & MVXPE_BARE_EN_MASK)
|
||||
|
||||
/* Ethernet Port Access Protect (MVXPE_EPAP) */
|
||||
#define MVXPE_EPAP_AC_NAC 0x0 /* No access allowed */
|
||||
#define MVXPE_EPAP_AC_RO 0x1 /* Read Only */
|
||||
#define MVXPE_EPAP_AC_FA 0x3 /* Full access (r/w) */
|
||||
#define MVXPE_EPAP_EPAR(win, ac) ((ac) << ((win) * 2))
|
||||
|
||||
/*
|
||||
* Global Miscellaneous Registers
|
||||
*/
|
||||
/* PHY Address (MVXPE_PHYADDR) */
|
||||
#define MVXPE_PHYADDR_PHYAD(phy) ((phy) & 0x1f)
|
||||
#define MVXPE_PHYADDR_GET_PHYAD(reg) ((reg) & 0x1f)
|
||||
|
||||
/* SMI register fields (MVXPE_SMI) */
|
||||
#define MVXPE_SMI_DATA_MASK 0x0000ffff
|
||||
#define MVXPE_SMI_PHYAD(phy) (((phy) & 0x1f) << 16)
|
||||
#define MVXPE_SMI_REGAD(reg) (((reg) & 0x1f) << 21)
|
||||
#define MVXPE_SMI_OPCODE_WRITE (0 << 26)
|
||||
#define MVXPE_SMI_OPCODE_READ (1 << 26)
|
||||
#define MVXPE_SMI_READVALID (1 << 27)
|
||||
#define MVXPE_SMI_BUSY (1 << 28)
|
||||
|
||||
/* Ethernet Unit Default ID (MVXPE_EUDID) */
|
||||
#define MVXPE_EUDID_DIDR_MASK 0x0000000f
|
||||
#define MVXPE_EUDID_DIDR(id) ((id) & 0x0f)
|
||||
#define MVXPE_EUDID_DATTR_MASK 0x00000ff0
|
||||
#define MVXPE_EUDID_DATTR(attr) (((attr) & 0xff) << 4)
|
||||
|
||||
/* Ethernet Unit Interrupt Cause (MVXPE_EUIC) */
|
||||
#define MVXPE_EUIC_ETHERINTSUM (1 << 0)
|
||||
#define MVXPE_EUIC_PARITY (1 << 1)
|
||||
#define MVXPE_EUIC_ADDRVIOL (1 << 2)
|
||||
#define MVXPE_EUIC_ADDRVNOMATCH (1 << 3)
|
||||
#define MVXPE_EUIC_SMIDONE (1 << 4)
|
||||
#define MVXPE_EUIC_COUNTWA (1 << 5)
|
||||
#define MVXPE_EUIC_INTADDRERR (1 << 7)
|
||||
#define MVXPE_EUIC_PORT0DPERR (1 << 9)
|
||||
#define MVXPE_EUIC_TOPDPERR (1 << 12)
|
||||
|
||||
/* Ethernet Unit Internal Addr Error (MVXPE_EUIAE) */
|
||||
#define MVXPE_EUIAE_INTADDR_MASK 0x000001ff
|
||||
#define MVXPE_EUIAE_INTADDR(addr) ((addr) & 0x1ff)
|
||||
#define MVXPE_EUIAE_GET_INTADDR(addr) ((addr) & 0x1ff)
|
||||
|
||||
/* Ethernet Unit Control (MVXPE_EUC) */
|
||||
#define MVXPE_EUC_POLLING (1 << 1)
|
||||
#define MVXPE_EUC_PORTRESET (1 << 24)
|
||||
#define MVXPE_EUC_RAMSINITIALIZATIONCOMPLETED (1 << 25)
|
||||
|
||||
/*
|
||||
* Miscellaneous Registers
|
||||
*/
|
||||
/* SDMA Configuration (MVXPE_SDC) */
|
||||
#define MVXPE_SDC_RXBSZ(x) ((x) << 1)
|
||||
#define MVXPE_SDC_RXBSZ_MASK MVXPE_SDC_RXBSZ(7)
|
||||
#define MVXPE_SDC_RXBSZ_1_64BITWORDS MVXPE_SDC_RXBSZ(0)
|
||||
#define MVXPE_SDC_RXBSZ_2_64BITWORDS MVXPE_SDC_RXBSZ(1)
|
||||
#define MVXPE_SDC_RXBSZ_4_64BITWORDS MVXPE_SDC_RXBSZ(2)
|
||||
#define MVXPE_SDC_RXBSZ_8_64BITWORDS MVXPE_SDC_RXBSZ(3)
|
||||
#define MVXPE_SDC_RXBSZ_16_64BITWORDS MVXPE_SDC_RXBSZ(4)
|
||||
#define MVXPE_SDC_BLMR (1 << 4)
|
||||
#define MVXPE_SDC_BLMT (1 << 5)
|
||||
#define MVXPE_SDC_SWAPMODE (1 << 6)
|
||||
#define MVXPE_SDC_TXBSZ(x) ((x) << 22)
|
||||
#define MVXPE_SDC_TXBSZ_MASK MVXPE_SDC_TXBSZ(7)
|
||||
#define MVXPE_SDC_TXBSZ_1_64BITWORDS MVXPE_SDC_TXBSZ(0)
|
||||
#define MVXPE_SDC_TXBSZ_2_64BITWORDS MVXPE_SDC_TXBSZ(1)
|
||||
#define MVXPE_SDC_TXBSZ_4_64BITWORDS MVXPE_SDC_TXBSZ(2)
|
||||
#define MVXPE_SDC_TXBSZ_8_64BITWORDS MVXPE_SDC_TXBSZ(3)
|
||||
#define MVXPE_SDC_TXBSZ_16_64BITWORDS MVXPE_SDC_TXBSZ(4)
|
||||
|
||||
/*
|
||||
* Networking Controller Miscellaneous Registers
|
||||
*/
|
||||
/* Port Acceleration Mode (MVXPE_PACC) */
|
||||
#define MVXPE_PACC_ACCELERATIONMODE_MASK 0x7
|
||||
#define MVXPE_PACC_ACCELERATIONMODE_EDM 0x1 /* Enhanced Desc Mode */
|
||||
|
||||
/* Port Version (MVXPE_PV) */
|
||||
#define MVXPE_PV_VERSION_MASK 0xff
|
||||
#define MVXPE_PV_VERSION(v) ((v) & 0xff)
|
||||
#define MVXPE_PV_GET_VERSION(reg) ((reg) & 0xff)
|
||||
|
||||
/*
|
||||
* Rx DMA Hardware Parser Registers
|
||||
*/
|
||||
/* Ether Type Priority (MVXPE_ETP) */
|
||||
#define MVXPE_ETP_ETHERTYPEPRIEN (1 << 0) /* EtherType Prio Ena */
|
||||
#define MVXPE_ETP_ETHERTYPEPRIFRSTEN (1 << 1)
|
||||
#define MVXPE_ETP_ETHERTYPEPRIQ (0x7 << 2) /*EtherType Prio Queue*/
|
||||
#define MVXPE_ETP_ETHERTYPEPRIVAL (0xffff << 5) /*EtherType Prio Value*/
|
||||
#define MVXPE_ETP_FORCEUNICSTHIT (1 << 21) /* Force Unicast hit */
|
||||
|
||||
/* Destination Address Filter Registers (MVXPE_DF{SM,OM,U}T) */
|
||||
#define MVXPE_DF(n, x) ((x) << (8 * (n)))
|
||||
#define MVXPE_DF_PASS (1 << 0)
|
||||
#define MVXPE_DF_QUEUE(q) ((q) << 1)
|
||||
#define MVXPE_DF_QUEUE_ALL ((7) << 1)
|
||||
#define MVXPE_DF_QUEUE_MASK ((7) << 1)
|
||||
|
||||
/*
|
||||
* Rx DMA Miscellaneous Registers
|
||||
*/
|
||||
/* Port Rx Minimal Frame Size (MVXPE_PMFS) */
|
||||
#define MVXPE_PMFS_RXMFS(rxmfs) (((rxmfs) - 40) & 0x7c)
|
||||
|
||||
/* Receive Queue Command (MVXPE_RQC) */
|
||||
#define MVXPE_RQC_EN_MASK (0xff << 0) /* Enable Q */
|
||||
#define MVXPE_RQC_ENQ(q) (1 << (0 + (q)))
|
||||
#define MVXPE_RQC_EN(n) ((n) << 0)
|
||||
#define MVXPE_RQC_DIS_MASK (0xff << 8) /* Disable Q */
|
||||
#define MVXPE_RQC_DISQ(q) (1 << (8 + (n)))
|
||||
#define MVXPE_RQC_DIS(n) ((n) << 8)
|
||||
|
||||
/*
|
||||
* Rx DMA Networking Controller Miscellaneous Registers
|
||||
*/
|
||||
/* Port RX queues Configuration (MVXPE_PRXC) */
|
||||
#define MVXPE_PRXC_PACKETOFFSET(o) (((o) & 0xf) << 8)
|
||||
|
||||
/* Port RX queues Snoop (MVXPE_PRXSNP) */
|
||||
#define MVXPE_PRXSNP_SNOOPNOOFBYTES(b) (((b) & 0x3fff) << 0)
|
||||
#define MVXPE_PRXSNP_L2DEPOSITNOOFBYTES(b) (((b) & 0x3fff) << 16)
|
||||
|
||||
/* Port RX queues Descriptors Queue Size (MVXPE_PRXDQS) */
|
||||
#define MVXPE_PRXDQS_DESCRIPTORSQUEUESIZE(s) (((s) & 0x3fff) << 0)
|
||||
#define MVXPE_PRXDQS_BUFFERSIZE(s) (((s) & 0x1fff) << 19)
|
||||
|
||||
/* Port RX queues Descriptors Queue Threshold (MVXPE_PRXDQTH) */
|
||||
/* Occupied Descriptors Threshold */
|
||||
#define MVXPE_PRXDQTH_ODT(x) (((x) & 0x3fff) << 0)
|
||||
/* Non Occupied Descriptors Threshold */
|
||||
#define MVXPE_PRXDQTH_NODT(x) (((x) & 0x3fff) << 16)
|
||||
|
||||
/* Port RX queues Status (MVXPE_PRXS) */
|
||||
/* Occupied Descriptors Counter */
|
||||
#define MVXPE_PRXS_ODC(x) (((x) & 0x3fff) << 0)
|
||||
/* Non Occupied Descriptors Counter */
|
||||
#define MVXPE_PRXS_NODC(x) (((x) & 0x3fff) << 16)
|
||||
#define MVXPE_PRXS_GET_ODC(reg) (((reg) >> 0) & 0x3fff)
|
||||
#define MVXPE_PRXS_GET_NODC(reg) (((reg) >> 16) & 0x3fff)
|
||||
|
||||
/* Port RX queues Status Update (MVXPE_PRXSU) */
|
||||
#define MVXPE_PRXSU_NOOFPROCESSEDDESCRIPTORS(x) (((x) & 0xff) << 0)
|
||||
#define MVXPE_PRXSU_NOOFNEWDESCRIPTORS(x) (((x) & 0xff) << 16)
|
||||
|
||||
/* Port RX Initialization (MVXPE_PRXINIT) */
|
||||
#define MVXPE_PRXINIT_RXDMAINIT (1 << 0)
|
||||
|
||||
/*
|
||||
* Rx DMA Wake on LAN Registers
|
||||
*/
|
||||
/* XXX: not implemented yet */
|
||||
|
||||
/*
|
||||
* Tx DMA Miscellaneous Registers
|
||||
*/
|
||||
/* Transmit Queue Command (MVXPE_TQC) */
|
||||
#define MVXPE_TQC_EN_MASK (0xff << 0)
|
||||
#define MVXPE_TQC_ENQ(q) (1 << ((q) + 0))/* Enable Q */
|
||||
#define MVXPE_TQC_EN(n) ((n) << 0)
|
||||
#define MVXPE_TQC_DIS_MASK (0xff << 8)
|
||||
#define MVXPE_TQC_DISQ(q) (1 << ((q) + 8))/* Disable Q */
|
||||
#define MVXPE_TQC_DIS(n) ((n) << 8)
|
||||
|
||||
/*
|
||||
* Tx DMA Networking Controller Miscellaneous Registers
|
||||
*/
|
||||
/* Port TX queues Descriptors Queue Size (MVXPE_PTXDQS) */
|
||||
/* Descriptors Queue Size */
|
||||
#define MVXPE_PTXDQS_DQS_MASK (0x3fff << 0)
|
||||
#define MVXPE_PTXDQS_DQS(x) (((x) & 0x3fff) << 0)
|
||||
/* Transmitted Buffer Threshold */
|
||||
#define MVXPE_PTXDQS_TBT_MASK (0x3fff << 16)
|
||||
#define MVXPE_PTXDQS_TBT(x) (((x) & 0x3fff) << 16)
|
||||
|
||||
/* Port TX queues Status (MVXPE_PTXS) */
|
||||
/* Transmitted Buffer Counter */
|
||||
#define MVXPE_PTXS_TBC(x) (((x) & 0x3fff) << 16)
|
||||
|
||||
#define MVXPE_PTXS_GET_TBC(reg) (((reg) >> 16) & 0x3fff)
|
||||
/* Pending Descriptors Counter */
|
||||
#define MVXPE_PTXS_PDC(x) ((x) & 0x3fff)
|
||||
#define MVXPE_PTXS_GET_PDC(x) ((x) & 0x3fff)
|
||||
|
||||
/* Port TX queues Status Update (MVXPE_PTXSU) */
|
||||
/* Number Of Written Descriptoes */
|
||||
#define MVXPE_PTXSU_NOWD(x) (((x) & 0xff) << 0)
|
||||
/* Number Of Released Buffers */
|
||||
#define MVXPE_PTXSU_NORB(x) (((x) & 0xff) << 16)
|
||||
|
||||
/* TX Transmitted Buffers Counter (MVXPE_TXTBC) */
|
||||
/* Transmitted Buffers Counter */
|
||||
#define MVXPE_TXTBC_TBC(x) (((x) & 0x3fff) << 16)
|
||||
|
||||
/* Port TX Initialization (MVXPE_PTXINIT) */
|
||||
#define MVXPE_PTXINIT_TXDMAINIT (1 << 0)
|
||||
|
||||
/*
|
||||
* Tx DMA Packet Modification Registers
|
||||
*/
|
||||
/* XXX: not implemeted yet */
|
||||
|
||||
/*
|
||||
* Tx DMA Queue Arbiter Registers (Version 1 )
|
||||
*/
|
||||
/* XXX: not implemented yet */
|
||||
/* Transmit Queue Fixed Priority Configuration */
|
||||
#define MVXPE_TQFPC_EN(q) (1 << (q))
|
||||
|
||||
|
||||
/*
|
||||
* RX_TX DMA Registers
|
||||
*/
|
||||
/* Port Configuration (MVXPE_PXC) */
|
||||
#define MVXPE_PXC_UPM (1 << 0) /* Uni Promisc mode */
|
||||
#define MVXPE_PXC_RXQ(q) ((q) << 1)
|
||||
#define MVXPE_PXC_RXQ_MASK MVXPE_PXC_RXQ(7)
|
||||
#define MVXPE_PXC_RXQARP(q) ((q) << 4)
|
||||
#define MVXPE_PXC_RXQARP_MASK MVXPE_PXC_RXQARP(7)
|
||||
#define MVXPE_PXC_RB (1 << 7) /* Rej mode of MAC */
|
||||
#define MVXPE_PXC_RBIP (1 << 8)
|
||||
#define MVXPE_PXC_RBARP (1 << 9)
|
||||
#define MVXPE_PXC_AMNOTXES (1 << 12)
|
||||
#define MVXPE_PXC_RBARPF (1 << 13)
|
||||
#define MVXPE_PXC_TCPCAPEN (1 << 14)
|
||||
#define MVXPE_PXC_UDPCAPEN (1 << 15)
|
||||
#define MVXPE_PXC_TCPQ(q) ((q) << 16)
|
||||
#define MVXPE_PXC_TCPQ_MASK MVXPE_PXC_TCPQ(7)
|
||||
#define MVXPE_PXC_UDPQ(q) ((q) << 19)
|
||||
#define MVXPE_PXC_UDPQ_MASK MVXPE_PXC_UDPQ(7)
|
||||
#define MVXPE_PXC_BPDUQ(q) ((q) << 22)
|
||||
#define MVXPE_PXC_BPDUQ_MASK MVXPE_PXC_BPDUQ(7)
|
||||
#define MVXPE_PXC_RXCS (1 << 25)
|
||||
|
||||
/* Port Configuration Extend (MVXPE_PXCX) */
|
||||
#define MVXPE_PXCX_SPAN (1 << 1)
|
||||
#define MVXPE_PXCX_TXCRCDIS (1 << 3)
|
||||
|
||||
/* Marvell Header (MVXPE_MH) */
|
||||
#define MVXPE_MH_MHEN (1 << 0)
|
||||
#define MVXPE_MH_DAPREFIX (0x3 << 1)
|
||||
#define MVXPE_MH_SPID (0xf << 4)
|
||||
#define MVXPE_MH_MHMASK (0x3 << 8)
|
||||
#define MVXPE_MH_MHMASK_8QUEUES (0x0 << 8)
|
||||
#define MVXPE_MH_MHMASK_4QUEUES (0x1 << 8)
|
||||
#define MVXPE_MH_MHMASK_2QUEUES (0x3 << 8)
|
||||
#define MVXPE_MH_DSAEN_MASK (0x3 << 10)
|
||||
#define MVXPE_MH_DSAEN_DISABLE (0x0 << 10)
|
||||
#define MVXPE_MH_DSAEN_NONEXTENDED (0x1 << 10)
|
||||
#define MVXPE_MH_DSAEN_EXTENDED (0x2 << 10)
|
||||
|
||||
/*
|
||||
* Serial(SMI/MII) Registers
|
||||
*/
|
||||
/* Port Seiral Control0 (MVXPE_PSC0) */
|
||||
#define MVXPE_PSC0_FORCE_FC_MASK (0x3 << 5)
|
||||
#define MVXPE_PSC0_FORCE_FC(fc) (((fc) & 0x3) << 5)
|
||||
#define MVXPE_PSC0_FORCE_FC_PAUSE MVXPE_PSC0_FORCE_FC(0x1)
|
||||
#define MVXPE_PSC0_FORCE_FC_NO_PAUSE MVXPE_PSC0_FORCE_FC(0x0)
|
||||
#define MVXPE_PSC0_FORCE_BP_MASK (0x3 << 7)
|
||||
#define MVXPE_PSC0_FORCE_BP(fc) (((fc) & 0x3) << 5)
|
||||
#define MVXPE_PSC0_FORCE_BP_JAM MVXPE_PSC0_FORCE_BP(0x1)
|
||||
#define MVXPE_PSC0_FORCE_BP_NO_JAM MVXPE_PSC0_FORCE_BP(0x0)
|
||||
#define MVXPE_PSC0_DTE_ADV (1 << 14)
|
||||
#define MVXPE_PSC0_IGN_RXERR (1 << 28)
|
||||
#define MVXPE_PSC0_IGN_COLLISION (1 << 29)
|
||||
#define MVXPE_PSC0_IGN_CARRIER (1 << 30)
|
||||
|
||||
/* Ethernet Port Status0 (MVXPE_PS0) */
|
||||
#define MVXPE_PS0_TXINPROG (1 << 0)
|
||||
#define MVXPE_PS0_TXFIFOEMP (1 << 8)
|
||||
#define MVXPE_PS0_RXFIFOEMPTY (1 << 16)
|
||||
|
||||
/*
|
||||
* Gigabit Ethernet MAC Serial Parameters Configuration Registers
|
||||
*/
|
||||
#define MVXPE_PSPC_MUST_SET (1 << 3 | 1 << 4 | 1 << 5 | 0x23 << 6)
|
||||
#define MVXPE_PSP1C_MUST_SET (1 << 0 | 1 << 1 | 1 << 2)
|
||||
|
||||
/*
|
||||
* Gigabit Ethernet Auto-Negotiation Configuration Registers
|
||||
*/
|
||||
/* Port Auto-Negotiation Configuration (MVXPE_PANC) */
|
||||
#define MVXPE_PANC_FORCELINKFAIL (1 << 0)
|
||||
#define MVXPE_PANC_FORCELINKPASS (1 << 1)
|
||||
#define MVXPE_PANC_INBANDANEN (1 << 2)
|
||||
#define MVXPE_PANC_INBANDANBYPASSEN (1 << 3)
|
||||
#define MVXPE_PANC_INBANDRESTARTAN (1 << 4)
|
||||
#define MVXPE_PANC_SETMIISPEED (1 << 5)
|
||||
#define MVXPE_PANC_SETGMIISPEED (1 << 6)
|
||||
#define MVXPE_PANC_ANSPEEDEN (1 << 7)
|
||||
#define MVXPE_PANC_SETFCEN (1 << 8)
|
||||
#define MVXPE_PANC_PAUSEADV (1 << 9)
|
||||
#define MVXPE_PANC_ANFCEN (1 << 11)
|
||||
#define MVXPE_PANC_SETFULLDX (1 << 12)
|
||||
#define MVXPE_PANC_ANDUPLEXEN (1 << 13)
|
||||
#define MVXPE_PANC_MUSTSET (1 << 15)
|
||||
|
||||
/*
|
||||
* Gigabit Ethernet MAC Control Registers
|
||||
*/
|
||||
/* Port MAC Control 0 (MVXPE_PMACC0) */
|
||||
#define MVXPE_PMACC0_PORTEN (1 << 0)
|
||||
#define MVXPE_PMACC0_PORTTYPE (1 << 1)
|
||||
#define MVXPE_PMACC0_FRAMESIZELIMIT(x) ((((x) >> 1) & 0x7ffc) << 2)
|
||||
#define MVXPE_PMACC0_MUSTSET (1 << 15)
|
||||
|
||||
/* Port MAC Control 1 (MVXPE_PMACC1) */
|
||||
#define MVXPE_PMACC1_PCSLB (1 << 6)
|
||||
|
||||
/* Port MAC Control 2 (MVXPE_PMACC2) */
|
||||
#define MVXPE_PMACC2_PCSEN (1 << 3)
|
||||
#define MVXPE_PMACC2_RGMIIEN (1 << 4)
|
||||
#define MVXPE_PMACC2_PADDINGDIS (1 << 5)
|
||||
#define MVXPE_PMACC2_PORTMACRESET (1 << 6)
|
||||
#define MVXPE_PMACC2_PRBSCHECKEN (1 << 10)
|
||||
#define MVXPE_PMACC2_PRBSGENEN (1 << 11)
|
||||
#define MVXPE_PMACC2_SDTT_MASK (3 << 12) /* Select Data To Transmit */
|
||||
#define MVXPE_PMACC2_SDTT_RM (0 << 12) /* Regular Mode */
|
||||
#define MVXPE_PMACC2_SDTT_PRBS (1 << 12) /* PRBS Mode */
|
||||
#define MVXPE_PMACC2_SDTT_ZC (2 << 12) /* Zero Constant */
|
||||
#define MVXPE_PMACC2_SDTT_OC (3 << 12) /* One Constant */
|
||||
#define MVXPE_PMACC2_MUSTSET (3 << 14)
|
||||
|
||||
/* Port MAC Control 3 (MVXPE_PMACC3) */
|
||||
#define MVXPE_PMACC3_IPG_MASK 0x7f80
|
||||
|
||||
/*
|
||||
* Gigabit Ethernet MAC Interrupt Registers
|
||||
*/
|
||||
/* Port Interrupt Cause/Mask (MVXPE_PIC/MVXPE_PIM) */
|
||||
#define MVXPE_PI_INTSUM (1 << 0)
|
||||
#define MVXPE_PI_LSC (1 << 1) /* LinkStatus Change */
|
||||
#define MVXPE_PI_ACOP (1 << 2) /* AnCompleted OnPort */
|
||||
#define MVXPE_PI_AOOR (1 << 5) /* AddressOut Of Range */
|
||||
#define MVXPE_PI_SSC (1 << 6) /* SyncStatus Change */
|
||||
#define MVXPE_PI_PRBSEOP (1 << 7) /* QSGMII PRBS error */
|
||||
#define MVXPE_PI_MIBCWA (1 << 15) /* MIB counter wrap around */
|
||||
#define MVXPE_PI_QSGMIIPRBSE (1 << 10) /* QSGMII PRBS error */
|
||||
#define MVXPE_PI_PCSRXPRLPI (1 << 11) /* PCS Rx path received LPI*/
|
||||
#define MVXPE_PI_PCSTXPRLPI (1 << 12) /* PCS Tx path received LPI*/
|
||||
#define MVXPE_PI_MACRXPRLPI (1 << 13) /* MAC Rx path received LPI*/
|
||||
#define MVXPE_PI_MIBCCD (1 << 14) /* MIB counters copy done */
|
||||
|
||||
/*
|
||||
* Gigabit Ethernet MAC Low Power Idle Registers
|
||||
*/
|
||||
/* LPI Control 0 (MVXPE_LPIC0) */
|
||||
#define MVXPE_LPIC0_LILIMIT(x) (((x) & 0xff) << 0)
|
||||
#define MVXPE_LPIC0_TSLIMIT(x) (((x) & 0xff) << 8)
|
||||
|
||||
/* LPI Control 1 (MVXPE_LPIC1) */
|
||||
#define MVXPE_LPIC1_LPIRE (1 << 0) /* LPI request enable */
|
||||
#define MVXPE_LPIC1_LPIRF (1 << 1) /* LPI request force */
|
||||
#define MVXPE_LPIC1_LPIMM (1 << 2) /* LPI manual mode */
|
||||
#define MVXPE_LPIC1_TWLIMIT(x) (((x) & 0xfff) << 4)
|
||||
|
||||
/* LPI Control 2 (MVXPE_LPIC2) */
|
||||
#define MVXPE_LPIC2_MUSTSET 0x17d
|
||||
|
||||
/* LPI Status (MVXPE_LPIS) */
|
||||
#define MVXPE_LPIS_PCSRXPLPIS (1 << 0) /* PCS Rx path LPI status */
|
||||
#define MVXPE_LPIS_PCSTXPLPIS (1 << 1) /* PCS Tx path LPI status */
|
||||
#define MVXPE_LPIS_MACRXPLPIS (1 << 2)/* MAC Rx path LP idle status */
|
||||
#define MVXPE_LPIS_MACTXPLPWS (1 << 3)/* MAC Tx path LP wait status */
|
||||
#define MVXPE_LPIS_MACTXPLPIS (1 << 4)/* MAC Tx path LP idle status */
|
||||
|
||||
/*
|
||||
* Gigabit Ethernet MAC PRBS Check Status Registers
|
||||
*/
|
||||
/* Port PRBS Status (MVXPE_PPRBSS) */
|
||||
#define MVXPE_PPRBSS_PRBSCHECKLOCKED (1 << 0)
|
||||
#define MVXPE_PPRBSS_PRBSCHECKRDY (1 << 1)
|
||||
|
||||
/*
|
||||
* Gigabit Ethernet MAC Status Registers
|
||||
*/
|
||||
/* Port Status Register (MVXPE_PSR) */
|
||||
#define MVXPE_PSR_LINKUP (1 << 0)
|
||||
#define MVXPE_PSR_GMIISPEED (1 << 1)
|
||||
#define MVXPE_PSR_MIISPEED (1 << 2)
|
||||
#define MVXPE_PSR_FULLDX (1 << 3)
|
||||
#define MVXPE_PSR_RXFCEN (1 << 4)
|
||||
#define MVXPE_PSR_TXFCEN (1 << 5)
|
||||
#define MVXPE_PSR_PRP (1 << 6) /* Port Rx Pause */
|
||||
#define MVXPE_PSR_PTP (1 << 7) /* Port Tx Pause */
|
||||
#define MVXPE_PSR_PDP (1 << 8) /*Port is Doing Back-Pressure*/
|
||||
#define MVXPE_PSR_SYNCFAIL10MS (1 << 10)
|
||||
#define MVXPE_PSR_ANDONE (1 << 11)
|
||||
#define MVXPE_PSR_IBANBA (1 << 12) /* InBand AutoNeg BypassAct */
|
||||
#define MVXPE_PSR_SYNCOK (1 << 14)
|
||||
|
||||
/*
|
||||
* Networking Controller Interrupt Registers
|
||||
*/
|
||||
/* Port RX_TX Interrupt Threshold */
|
||||
#define MVXPE_PRXITTH_RITT(t) ((t) & 0xffffff)
|
||||
|
||||
/* Port RX_TX Threshold Interrupt Cause/Mask (MVXPE_PRXTXTIC/MVXPE_PRXTXTIM) */
|
||||
#define MVXPE_PRXTXTI_TBTCQ(q) (1 << ((q) + 0))
|
||||
#define MVXPE_PRXTXTI_TBTCQ_MASK (0xff << 0)
|
||||
/* Tx Buffer Threshold Cross Queue*/
|
||||
#define MVXPE_PRXTXTI_RBICTAPQ(q) (1 << ((q) + 8))
|
||||
#define MVXPE_PRXTXTI_RBICTAPQ_MASK (0xff << 8)
|
||||
/* Rx Buffer Int. Coaleasing Th. Pri. Alrt Q */
|
||||
#define MVXPE_PRXTXTI_RDTAQ(q) (1 << ((q) + 16))
|
||||
#define MVXPE_PRXTXTI_RDTAQ_MASK (0xff << 16)
|
||||
/* Rx Descriptor Threshold Alert Queue*/
|
||||
#define MVXPE_PRXTXTI_PRXTXICSUMMARY (1 << 29) /* PRXTXI summary */
|
||||
#define MVXPE_PRXTXTI_PTXERRORSUMMARY (1 << 30) /* PTEXERROR summary */
|
||||
#define MVXPE_PRXTXTI_PMISCICSUMMARY (1 << 31) /* PMISCIC summary */
|
||||
|
||||
/* Port RX_TX Interrupt Cause/Mask (MVXPE_PRXTXIC/MVXPE_PRXTXIM) */
|
||||
#define MVXPE_PRXTXI_TBRQ(q) (1 << ((q) + 0))
|
||||
#define MVXPE_PRXTXI_TBRQ_MASK (0xff << 0)
|
||||
#define MVXPE_PRXTXI_RPQ(q) (1 << ((q) + 8))
|
||||
#define MVXPE_PRXTXI_RPQ_MASK (0xff << 8)
|
||||
#define MVXPE_PRXTXI_RREQ(q) (1 << ((q) + 16))
|
||||
#define MVXPE_PRXTXI_RREQ_MASK (0xff << 16)
|
||||
#define MVXPE_PRXTXI_PRXTXTHICSUMMARY (1 << 29)
|
||||
#define MVXPE_PRXTXI_PTXERRORSUMMARY (1 << 30)
|
||||
#define MVXPE_PRXTXI_PMISCICSUMMARY (1 << 31)
|
||||
|
||||
/* Port Misc Interrupt Cause/Mask (MVXPE_PMIC/MVXPE_PMIM) */
|
||||
#define MVXPE_PMI_PHYSTATUSCHNG (1 << 0)
|
||||
#define MVXPE_PMI_LINKCHANGE (1 << 1)
|
||||
#define MVXPE_PMI_IAE (1 << 7) /* Internal Address Error */
|
||||
#define MVXPE_PMI_RXOVERRUN (1 << 8)
|
||||
#define MVXPE_PMI_RXCRCERROR (1 << 9)
|
||||
#define MVXPE_PMI_RXLARGEPACKET (1 << 10)
|
||||
#define MVXPE_PMI_TXUNDRN (1 << 11)
|
||||
#define MVXPE_PMI_PRBSERROR (1 << 12)
|
||||
#define MVXPE_PMI_SRSE (1 << 14) /* SerdesRealignSyncError */
|
||||
#define MVXPE_PMI_TREQ(q) (1 << ((q) + 24)) /* TxResourceErrorQ */
|
||||
#define MVXPE_PMI_TREQ_MASK (0xff << 24) /* TxResourceErrorQ */
|
||||
|
||||
/* Port Interrupt Enable (MVXPE_PIE) */
|
||||
#define MVXPE_PIE_RXPKTINTRPTENB(q) (1 << ((q) + 0))
|
||||
#define MVXPE_PIE_TXPKTINTRPTENB(q) (1 << ((q) + 8))
|
||||
#define MVXPE_PIE_RXPKTINTRPTENB_MASK (0xff << 0)
|
||||
#define MVXPE_PIE_TXPKTINTRPTENB_MASK (0xff << 8)
|
||||
|
||||
/*
|
||||
* Miscellaneous Interrupt Registers
|
||||
*/
|
||||
#define MVXPE_PEUIAE_ADDR_MASK (0x3fff)
|
||||
#define MVXPE_PEUIAE_ADDR(addr) ((addr) & 0x3fff)
|
||||
#define MVXPE_PEUIAE_GET_ADDR(reg) ((reg) & 0x3fff)
|
||||
|
||||
/*
|
||||
* SGMII PHY Registers
|
||||
*/
|
||||
/* Power and PLL Control (MVXPE_PPLLC) */
|
||||
#define MVXPE_PPLLC_REF_FREF_SEL_MASK (0xf << 0)
|
||||
#define MVXPE_PPLLC_PHY_MODE_MASK (7 << 5)
|
||||
#define MVXPE_PPLLC_PHY_MODE_SATA (0 << 5)
|
||||
#define MVXPE_PPLLC_PHY_MODE_SAS (1 << 5)
|
||||
#define MVXPE_PPLLC_PLL_LOCK (1 << 8)
|
||||
#define MVXPE_PPLLC_PU_DFE (1 << 10)
|
||||
#define MVXPE_PPLLC_PU_TX_INTP (1 << 11)
|
||||
#define MVXPE_PPLLC_PU_TX (1 << 12)
|
||||
#define MVXPE_PPLLC_PU_RX (1 << 13)
|
||||
#define MVXPE_PPLLC_PU_PLL (1 << 14)
|
||||
|
||||
/* Digital Loopback Enable (MVXPE_DLE) */
|
||||
#define MVXPE_DLE_LOCAL_SEL_BITS_MASK (3 << 10)
|
||||
#define MVXPE_DLE_LOCAL_SEL_BITS_10BITS (0 << 10)
|
||||
#define MVXPE_DLE_LOCAL_SEL_BITS_20BITS (1 << 10)
|
||||
#define MVXPE_DLE_LOCAL_SEL_BITS_40BITS (2 << 10)
|
||||
#define MVXPE_DLE_LOCAL_RXPHER_TO_TX_EN (1 << 12)
|
||||
#define MVXPE_DLE_LOCAL_ANA_TX2RX_LPBK_EN (1 << 13)
|
||||
#define MVXPE_DLE_LOCAL_DIG_TX2RX_LPBK_EN (1 << 14)
|
||||
#define MVXPE_DLE_LOCAL_DIG_RX2TX_LPBK_EN (1 << 15)
|
||||
|
||||
/* Reference Clock Select (MVXPE_RCS) */
|
||||
#define MVXPE_RCS_REFCLK_SEL (1 << 10)
|
||||
|
||||
/*
|
||||
* DMA descriptors
|
||||
*/
|
||||
struct mvxpe_tx_desc {
|
||||
/* LITTLE_ENDIAN */
|
||||
uint32_t command; /* off 0x00: commands */
|
||||
uint16_t l4ichk; /* initial checksum */
|
||||
uint16_t bytecnt; /* 0ff 0x04: buffer byte count */
|
||||
uint32_t bufptr; /* off 0x08: buffer ptr(PA) */
|
||||
uint32_t flags; /* off 0x0c: flags */
|
||||
uint32_t reserved0; /* off 0x10 */
|
||||
uint32_t reserved1; /* off 0x14 */
|
||||
uint32_t reserved2; /* off 0x18 */
|
||||
uint32_t reserved3; /* off 0x1c */
|
||||
};
|
||||
|
||||
struct mvxpe_rx_desc {
|
||||
/* LITTLE_ENDIAN */
|
||||
uint32_t status; /* status and flags */
|
||||
uint16_t reserved0;
|
||||
uint16_t bytecnt; /* buffer byte count */
|
||||
uint32_t bufptr; /* packet buffer pointer */
|
||||
uint32_t reserved1;
|
||||
uint32_t reserved2;
|
||||
uint16_t reserved3;
|
||||
uint16_t l4chk; /* L4 checksum */
|
||||
uint32_t reserved4;
|
||||
uint32_t reserved5;
|
||||
};
|
||||
|
||||
/*
|
||||
* Received pakcet command header:
|
||||
* network controller => software
|
||||
* the controller parse the packet and set some flags.
|
||||
*/
|
||||
#define MVXPE_RX_IPV4_FRAGMENT (1 << 31) /* Fragment Indicator */
|
||||
#define MVXPE_RX_L4_CHECKSUM_OK (1 << 30) /* L4 Checksum */
|
||||
/* bit 29 reserved */
|
||||
#define MVXPE_RX_U (1 << 28) /* Unknown Destination */
|
||||
#define MVXPE_RX_F (1 << 27) /* First buffer */
|
||||
#define MVXPE_RX_L (1 << 26) /* Last buffer */
|
||||
#define MVXPE_RX_IP_HEADER_OK (1 << 25) /* IP Header is OK */
|
||||
#define MVXPE_RX_L3_IP (1 << 24) /* IP Type 0:IP6 1:IP4 */
|
||||
#define MVXPE_RX_L2_EV2 (1 << 23) /* Ethernet v2 frame */
|
||||
#define MVXPE_RX_L4_MASK (3 << 21) /* L4 Type */
|
||||
#define MVXPE_RX_L4_TCP (0x00 << 21)
|
||||
#define MVXPE_RX_L4_UDP (0x01 << 21)
|
||||
#define MVXPE_RX_L4_OTH (0x10 << 21)
|
||||
#define MVXPE_RX_BPDU (1 << 20) /* BPDU frame */
|
||||
#define MVXPE_RX_VLAN (1 << 19) /* VLAN tag found */
|
||||
#define MVXPE_RX_EC_MASK (3 << 17) /* Error code */
|
||||
#define MVXPE_RX_EC_CE (0x00 << 17) /* CRC error */
|
||||
#define MVXPE_RX_EC_OR (0x01 << 17) /* FIFO overrun */
|
||||
#define MVXPE_RX_EC_MF (0x10 << 17) /* Max. frame len */
|
||||
#define MVXPE_RX_EC_RE (0x11 << 17) /* Resource error */
|
||||
#define MVXPE_RX_ES (1 << 16) /* Error summary */
|
||||
/* bit 15:0 reserved */
|
||||
|
||||
/*
|
||||
* Transmit packet command header:
|
||||
* software => network controller
|
||||
*/
|
||||
#define MVXPE_TX_CMD_L4_CHECKSUM_MASK (0x3 << 30) /* Do L4 Checksum */
|
||||
#define MVXPE_TX_CMD_L4_CHECKSUM_FRAG (0x0 << 30)
|
||||
#define MVXPE_TX_CMD_L4_CHECKSUM_NOFRAG (0x1 << 30)
|
||||
#define MVXPE_TX_CMD_L4_CHECKSUM_NONE (0x2 << 30)
|
||||
#define MVXPE_TX_CMD_PACKET_OFFSET_MASK (0x7f << 23) /* Payload offset */
|
||||
#define MVXPE_TX_CMD_W_PACKET_OFFSET(v) (((v) & 0x7f) << 23)
|
||||
/* bit 22 reserved */
|
||||
#define MVXPE_TX_CMD_F (1 << 21) /* First buffer */
|
||||
#define MVXPE_TX_CMD_L (1 << 20) /* Last buffer */
|
||||
#define MVXPE_TX_CMD_PADDING (1 << 19) /* Pad short frame */
|
||||
#define MVXPE_TX_CMD_IP4_CHECKSUM (1 << 18) /* Do IPv4 Checksum */
|
||||
#define MVXPE_TX_CMD_L3_TYPE (1 << 17) /* L3 Type 0:IP4, 1:IP6 */
|
||||
#define MVXPE_TX_CMD_L3_IP4 (0 << 17)
|
||||
#define MVXPE_TX_CMD_L3_IP6 (0 << 17)
|
||||
#define MVXPE_TX_CMD_L4_TYPE (1 << 16) /* L4 Type 0:TCP, 1:UDP */
|
||||
#define MVXPE_TX_CMD_L4_TCP (0 << 16)
|
||||
#define MVXPE_TX_CMD_L4_UDP (1 << 16)
|
||||
/* bit 15:13 reserved */
|
||||
#define MVXPE_TX_CMD_IP_HEADER_LEN_MASK (0x1f << 8) /* IP header len >> 2 */
|
||||
#define MVXPE_TX_CMD_W_IP_HEADER_LEN(v) (((v) & 0x1f) << 8)
|
||||
/* bit 7 reserved */
|
||||
#define MVXPE_TX_CMD_L3_OFFSET_MASK (0x7f << 0) /* offset of L3 hdr. */
|
||||
#define MVXPE_TX_CMD_W_L3_OFFSET(v) (((v) & 0x7f) << 0)
|
||||
|
||||
/*
|
||||
* Transmit pakcet extra attributes
|
||||
* and error status returned from network controller.
|
||||
*/
|
||||
#define MVXPE_TX_F_DSA_TAG (3 << 30) /* DSA Tag */
|
||||
/* bit 29:8 reserved */
|
||||
#define MVXPE_TX_F_MH_SEL (0xf << 4) /* Marvell Header */
|
||||
/* bit 3 reserved */
|
||||
#define MVXPE_TX_F_EC_MASK (3 << 1) /* Error code */
|
||||
#define MVXPE_TX_F_EC_LC (0x00 << 1) /* Late Collision */
|
||||
#define MVXPE_TX_F_EC_UR (0x01 << 1) /* Underrun */
|
||||
#define MVXPE_TX_F_EC_RL (0x10 << 1) /* Excess. Collision */
|
||||
#define MVXPE_TX_F_EC_RESERVED (0x11 << 1)
|
||||
#define MVXPE_TX_F_ES (1 << 0) /* Error summary */
|
||||
|
||||
#define MVXPE_ERROR_SUMMARY (1 << 0)
|
||||
#define MVXPE_BUFFER_OWNED_MASK (1 << 31)
|
||||
#define MVXPE_BUFFER_OWNED_BY_HOST (0 << 31)
|
||||
#define MVXPE_BUFFER_OWNED_BY_DMA (1 << 31)
|
||||
|
||||
#endif /* _IF_MVXPEREG_H_ */
|
||||
|
|
@ -0,0 +1,573 @@
|
|||
/* $NetBSD: if_mvxpevar.h,v 1.1 2015/05/03 14:38:10 hsuenaga Exp $ */
|
||||
/*
|
||||
* Copyright (c) 2015 Internet Initiative Japan Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
#ifndef _IF_MVXPEVAR_H_
|
||||
#define _IF_MVXPEVAR_H_
|
||||
/*
|
||||
* Comple options
|
||||
* XXX: use kernel config
|
||||
*/
|
||||
#define MVXPE_DEBUG 0
|
||||
#define MVXPE_EVENT_COUNTERS
|
||||
|
||||
/*
|
||||
* Limit of packet sizes.
|
||||
*/
|
||||
#define MVXPE_HWHEADER_SIZE 2 /* Marvell Header */
|
||||
#define MVXPE_MRU 2000 /* Max Receive Unit */
|
||||
#define MVXPE_MTU MVXPE_MRU /* Max Transmit Unit */
|
||||
|
||||
/*
|
||||
* Default limit of queue length
|
||||
*
|
||||
* queue 0 is lowest priority and queue 7 is highest priority.
|
||||
* IP packet is received on queue 7 by default.
|
||||
*
|
||||
* XXX: packet classifier is not implement yet
|
||||
*/
|
||||
#define MVXPE_RX_QUEUE_LIMIT_0 8
|
||||
#define MVXPE_RX_QUEUE_LIMIT_1 8
|
||||
#define MVXPE_RX_QUEUE_LIMIT_2 8
|
||||
#define MVXPE_RX_QUEUE_LIMIT_3 8
|
||||
#define MVXPE_RX_QUEUE_LIMIT_4 8
|
||||
#define MVXPE_RX_QUEUE_LIMIT_5 8
|
||||
#define MVXPE_RX_QUEUE_LIMIT_6 8
|
||||
#define MVXPE_RX_QUEUE_LIMIT_7 256
|
||||
|
||||
#define MVXPE_TX_QUEUE_LIMIT_0 256
|
||||
#define MVXPE_TX_QUEUE_LIMIT_1 8
|
||||
#define MVXPE_TX_QUEUE_LIMIT_2 8
|
||||
#define MVXPE_TX_QUEUE_LIMIT_3 8
|
||||
#define MVXPE_TX_QUEUE_LIMIT_4 8
|
||||
#define MVXPE_TX_QUEUE_LIMIT_5 8
|
||||
#define MVXPE_TX_QUEUE_LIMIT_6 8
|
||||
#define MVXPE_TX_QUEUE_LIMIT_7 8
|
||||
|
||||
/*
|
||||
* Device Register access
|
||||
*/
|
||||
#define MVXPE_READ(sc, reg) \
|
||||
bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg))
|
||||
#define MVXPE_WRITE(sc, reg, val) \
|
||||
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
|
||||
|
||||
#define MVXPE_READ_REGION(sc, reg, val, c) \
|
||||
bus_space_read_region_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val), (c))
|
||||
#define MVXPE_WRITE_REGION(sc, reg, val, c) \
|
||||
bus_space_write_region_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val), (c))
|
||||
|
||||
#define MVXPE_READ_MIB(sc, reg) \
|
||||
bus_space_read_4((sc)->sc_iot, (sc)->sc_mibh, (reg))
|
||||
|
||||
#define MVXPE_IS_LINKUP(sc) \
|
||||
(MVXPE_READ((sc), MVXPE_PSR) & MVXPE_PSR_LINKUP)
|
||||
|
||||
/*
|
||||
* EEE: Lower Power Idle config
|
||||
* Default timer is duration of MTU sized frame transmission.
|
||||
* The timer can be negotiated by LLDP protocol, but we have no
|
||||
* support.
|
||||
*/
|
||||
#define MVXPE_LPI_TS (MVXPE_MRU * 8 / 1000) /* [us] */
|
||||
#define MVXPE_LPI_TW (MVXPE_MRU * 8 / 1000) /* [us] */
|
||||
#define MVXPE_LPI_LI (MVXPE_MRU * 8 / 1000) /* [us] */
|
||||
|
||||
/*
|
||||
* DMA Descriptor
|
||||
*
|
||||
* the ethernet device has 8 rx/tx DMA queues. each of queue has its own
|
||||
* decriptor list. descriptors are simply index by counter inside the device.
|
||||
*/
|
||||
#define MVXPE_TX_RING_CNT 256
|
||||
#define MVXPE_TX_RING_MSK (MVXPE_TX_RING_CNT - 1)
|
||||
#define MVXPE_TX_RING_NEXT(x) (((x) + 1) & MVXPE_TX_RING_MSK)
|
||||
#define MVXPE_RX_RING_CNT 256
|
||||
#define MVXPE_RX_RING_MSK (MVXPE_RX_RING_CNT - 1)
|
||||
#define MVXPE_RX_RING_NEXT(x) (((x) + 1) & MVXPE_RX_RING_MSK)
|
||||
#define MVXPE_TX_SEGLIMIT 32
|
||||
|
||||
struct mvxpe_rx_ring {
|
||||
/* Real descriptors array. shared by RxDMA */
|
||||
struct mvxpe_rx_desc *rx_descriptors;
|
||||
bus_dmamap_t rx_descriptors_map;
|
||||
|
||||
/* Managment entries for each of descritors */
|
||||
struct mvxpe_rx_handle {
|
||||
struct mvxpe_rx_desc *rxdesc_va;
|
||||
off_t rxdesc_off; /* from rx_descriptors[0] */
|
||||
struct mvxpe_bm_chunk *chunk;
|
||||
} rx_handle[MVXPE_RX_RING_CNT];
|
||||
|
||||
/* locks */
|
||||
kmutex_t rx_ring_mtx;
|
||||
|
||||
/* Index */
|
||||
int rx_dma;
|
||||
int rx_cpu;
|
||||
|
||||
/* Limit */
|
||||
int rx_queue_len;
|
||||
int rx_queue_th_received;
|
||||
int rx_queue_th_free;
|
||||
int rx_queue_th_time; /* [Tclk] */
|
||||
};
|
||||
|
||||
struct mvxpe_tx_ring {
|
||||
/* Real descriptors array. shared by TxDMA */
|
||||
struct mvxpe_tx_desc *tx_descriptors;
|
||||
bus_dmamap_t tx_descriptors_map;
|
||||
|
||||
/* Managment entries for each of descritors */
|
||||
struct mvxpe_tx_handle {
|
||||
struct mvxpe_tx_desc *txdesc_va;
|
||||
off_t txdesc_off; /* from tx_descriptors[0] */
|
||||
struct mbuf *txdesc_mbuf;
|
||||
bus_dmamap_t txdesc_mbuf_map;
|
||||
} tx_handle[MVXPE_TX_RING_CNT];
|
||||
|
||||
/* locks */
|
||||
kmutex_t tx_ring_mtx;
|
||||
|
||||
/* Index */
|
||||
int tx_free_cnt;
|
||||
int tx_dma;
|
||||
int tx_cpu;
|
||||
|
||||
/* Limit */
|
||||
int tx_queue_len;
|
||||
int tx_queue_th_free;
|
||||
};
|
||||
|
||||
static inline int
|
||||
tx_counter_adv(int ctr, int n)
|
||||
{
|
||||
/* XXX: lock or atomic */
|
||||
ctr += n;
|
||||
while (ctr >= MVXPE_TX_RING_CNT)
|
||||
ctr -= MVXPE_TX_RING_CNT;
|
||||
|
||||
return ctr;
|
||||
}
|
||||
|
||||
static inline int
|
||||
rx_counter_adv(int ctr, int n)
|
||||
{
|
||||
/* XXX: lock or atomic */
|
||||
ctr += n;
|
||||
while (ctr >= MVXPE_TX_RING_CNT)
|
||||
ctr -= MVXPE_TX_RING_CNT;
|
||||
|
||||
return ctr;
|
||||
}
|
||||
|
||||
/*
|
||||
* Buffer alignement
|
||||
*/
|
||||
#define MVXPE_RXBUF_ALIGN 32 /* Cache line size */
|
||||
#define MVXPE_RXBUF_MASK (MVXPE_RXBUF_ALIGN - 1)
|
||||
#define MVXPE_BM_ADDR_ALIGN 32
|
||||
#define MVXPE_BM_ADDR_MASK (MVXPE_BM_ADDR_ALIGN - 1)
|
||||
|
||||
/*
|
||||
* Timeout control
|
||||
*/
|
||||
#define MVXPE_PHY_TIMEOUT 10000 /* msec */
|
||||
#define RX_DISABLE_TIMEOUT 0x1000000 /* times */
|
||||
#define TX_DISABLE_TIMEOUT 0x1000000 /* times */
|
||||
#define TX_FIFO_EMPTY_TIMEOUT 0x1000000 /* times */
|
||||
|
||||
/*
|
||||
* Event counter
|
||||
*/
|
||||
#ifdef MVXPE_EVENT_COUNTERS
|
||||
#define MVXPE_EVCNT_INCR(ev) (ev)->ev_count++
|
||||
#define MVXPE_EVCNT_ADD(ev, val) (ev)->ev_count += (val)
|
||||
#else
|
||||
#define MVXPE_EVCNT_INCR(ev) /* nothing */
|
||||
#define MVXPE_EVCNT_ADD(ev, val) /* nothing */
|
||||
#endif
|
||||
struct mvxpe_evcnt {
|
||||
/*
|
||||
* Master Interrupt Handler
|
||||
*/
|
||||
struct evcnt ev_i_rxtxth;
|
||||
struct evcnt ev_i_rxtx;
|
||||
struct evcnt ev_i_misc;
|
||||
|
||||
/*
|
||||
* RXTXTH Interrupt
|
||||
*/
|
||||
struct evcnt ev_rxtxth_txerr;
|
||||
|
||||
/*
|
||||
* MISC Interrupt
|
||||
*/
|
||||
struct evcnt ev_misc_phystatuschng;
|
||||
struct evcnt ev_misc_linkchange;
|
||||
struct evcnt ev_misc_iae;
|
||||
struct evcnt ev_misc_rxoverrun;
|
||||
struct evcnt ev_misc_rxcrc;
|
||||
struct evcnt ev_misc_rxlargepacket;
|
||||
struct evcnt ev_misc_txunderrun;
|
||||
struct evcnt ev_misc_prbserr;
|
||||
struct evcnt ev_misc_srse;
|
||||
struct evcnt ev_misc_txreq;
|
||||
|
||||
/*
|
||||
* RxTx Interrupt
|
||||
*/
|
||||
struct evcnt ev_rxtx_rreq;
|
||||
struct evcnt ev_rxtx_rpq;
|
||||
struct evcnt ev_rxtx_tbrq;
|
||||
struct evcnt ev_rxtx_rxtxth;
|
||||
struct evcnt ev_rxtx_txerr;
|
||||
struct evcnt ev_rxtx_misc;
|
||||
|
||||
/*
|
||||
* Link
|
||||
*/
|
||||
struct evcnt ev_link_up;
|
||||
struct evcnt ev_link_down;
|
||||
|
||||
/*
|
||||
* Rx Descriptor
|
||||
*/
|
||||
struct evcnt ev_rxd_ce;
|
||||
struct evcnt ev_rxd_or;
|
||||
struct evcnt ev_rxd_mf;
|
||||
struct evcnt ev_rxd_re;
|
||||
struct evcnt ev_rxd_scat;
|
||||
|
||||
/*
|
||||
* Tx Descriptor
|
||||
*/
|
||||
struct evcnt ev_txd_lc;
|
||||
struct evcnt ev_txd_ur;
|
||||
struct evcnt ev_txd_rl;
|
||||
struct evcnt ev_txd_oth;
|
||||
|
||||
/*
|
||||
* Status Registers
|
||||
*/
|
||||
struct evcnt ev_reg_pdfc; /* Rx Port Discard Frame Counter */
|
||||
struct evcnt ev_reg_pofc; /* Rx Port Overrun Frame Counter */
|
||||
struct evcnt ev_reg_txbadfcs; /* Tx BAD FCS Counter */
|
||||
struct evcnt ev_reg_txdropped; /* Tx Dropped Counter */
|
||||
struct evcnt ev_reg_lpic;
|
||||
|
||||
|
||||
/* Device Driver Errors */
|
||||
struct evcnt ev_drv_wdogsoft;
|
||||
struct evcnt ev_drv_txerr;
|
||||
struct evcnt ev_drv_rxq[MVXPE_QUEUE_SIZE];
|
||||
struct evcnt ev_drv_rxqe[MVXPE_QUEUE_SIZE];
|
||||
struct evcnt ev_drv_txq[MVXPE_QUEUE_SIZE];
|
||||
struct evcnt ev_drv_txqe[MVXPE_QUEUE_SIZE];
|
||||
};
|
||||
|
||||
/*
|
||||
* Debug
|
||||
*/
|
||||
#ifdef MVXPE_DEBUG
|
||||
#define DPRINTF(fmt, ...) \
|
||||
do { \
|
||||
if (mvxpe_debug >= 1) { \
|
||||
printf("%s: ", __func__); \
|
||||
printf((fmt), ##__VA_ARGS__); \
|
||||
} \
|
||||
} while (/*CONSTCOND*/0)
|
||||
#define DPRINTFN(level , fmt, ...) \
|
||||
do { \
|
||||
if (mvxpe_debug >= (level)) { \
|
||||
printf("%s: ", __func__); \
|
||||
printf((fmt), ##__VA_ARGS__); \
|
||||
} \
|
||||
} while (/*CONSTCOND*/0)
|
||||
#define DPRINTDEV(dev, level, fmt, ...) \
|
||||
do { \
|
||||
if (mvxpe_debug >= (level)) { \
|
||||
device_printf((dev), \
|
||||
"%s: "fmt , __func__, ##__VA_ARGS__); \
|
||||
} \
|
||||
} while (/*CONSTCOND*/0)
|
||||
#define DPRINTSC(sc, level, fmt, ...) \
|
||||
do { \
|
||||
device_t dev = (sc)->sc_dev; \
|
||||
if (mvxpe_debug >= (level)) { \
|
||||
device_printf(dev, \
|
||||
"%s: " fmt, __func__, ##__VA_ARGS__); \
|
||||
} \
|
||||
} while (/*CONSTCOND*/0)
|
||||
#define DPRINTIFNET(ifp, level, fmt, ...) \
|
||||
do { \
|
||||
const char *xname = (ifp)->if_xname; \
|
||||
if (mvxpe_debug >= (level)) { \
|
||||
printf("%s: %s: " fmt, xname, __func__, ##__VA_ARGS__);\
|
||||
} \
|
||||
} while (/*CONSTCOND*/0)
|
||||
#define DPRINTIFNET(ifp, level, fmt, ...) \
|
||||
do { \
|
||||
const char *xname = (ifp)->if_xname; \
|
||||
if (mvxpe_debug >= (level)) { \
|
||||
printf("%s: %s: " fmt, xname, __func__, ##__VA_ARGS__);\
|
||||
} \
|
||||
} while (/*CONSTCOND*/0)
|
||||
#define DPRINTPRXS(level, q) \
|
||||
do { \
|
||||
uint32_t _reg = MVXPE_READ(sc, MVXPE_PRXS(q)); \
|
||||
if (mvxpe_debug >= (level)) { \
|
||||
printf("PRXS(queue %d) %#x: Occupied %d, NoOccupied %d.\n", \
|
||||
q, _reg, MVXPE_PRXS_GET_ODC(_reg), \
|
||||
MVXPE_PRXS_GET_NODC(_reg)); \
|
||||
} \
|
||||
} while (/*CONSTCOND*/0)
|
||||
#else
|
||||
#define DPRINTF(fmt, ...)
|
||||
#define DPRINTFN(level, fmt, ...)
|
||||
#define DPRINTDEV(dev, level, fmt, ...)
|
||||
#define DPRINTSC(sc, level, fmt, ...)
|
||||
#define DPRINTIFNET(ifp, level, fmt, ...)
|
||||
#define DPRINTPRXS(level, reg)
|
||||
#endif
|
||||
|
||||
#define KASSERT_SC_MTX(sc) \
|
||||
KASSERT(mutex_owned(&(sc)->sc_mtx))
|
||||
#define KASSERT_BM_MTX(sc) \
|
||||
KASSERT(mutex_owned(&(sc)->sc_bm.bm_mtx))
|
||||
#define KASSERT_RX_MTX(sc, q) \
|
||||
KASSERT(mutex_owned(&(sc)->sc_rx_ring[(q)].rx_ring_mtx))
|
||||
#define KASSERT_TX_MTX(sc, q) \
|
||||
KASSERT(mutex_owned(&(sc)->sc_tx_ring[(q)].tx_ring_mtx))
|
||||
|
||||
/*
|
||||
* Configuration parameters
|
||||
*/
|
||||
struct mvxpe_conf {
|
||||
int cf_lpi; /* EEE Low Power IDLE enable */
|
||||
int cf_fc; /* Flow Control enable */
|
||||
};
|
||||
|
||||
/*
|
||||
* sysctl(9) parameters
|
||||
*/
|
||||
struct mvxpe_softc;
|
||||
struct mvxpe_sysctl_queue {
|
||||
struct mvxpe_softc *sc;
|
||||
int rxtx;
|
||||
int queue;
|
||||
};
|
||||
#define MVXPE_SYSCTL_RX 0
|
||||
#define MVXPE_SYSCTL_TX 1
|
||||
|
||||
struct mvxpe_sysctl_mib {
|
||||
struct mvxpe_softc *sc;
|
||||
int index;
|
||||
uint64_t counter;
|
||||
};
|
||||
|
||||
/*
|
||||
* Packet Buffer Header
|
||||
*
|
||||
* this chunks may be managed by H/W Buffer Manger(BM) device,
|
||||
* but there is no device driver yet.
|
||||
*
|
||||
* +----------------+ bm_buf
|
||||
* |chunk header | |
|
||||
* +----------------+ | | |chunk->buf_off
|
||||
* |mbuf (M_EXT set)|<--------|struct mbuf *m | V
|
||||
* +----------------+ +----------------+ chunk->buf_va/buf_pa
|
||||
* | m_ext.ext_buf|-------->|packet buffer | |
|
||||
* +----------------+ | | |chunk->buf_size
|
||||
* | | V
|
||||
* +----------------+
|
||||
* |chunk header |
|
||||
* |.... |
|
||||
*/
|
||||
#define MVXPE_BM_SLOTS \
|
||||
(MVXPE_RX_RING_CNT * (MVXPE_QUEUE_SIZE + 1))
|
||||
#define MVXPE_BM_SIZE \
|
||||
(MVXPE_MRU + MVXPE_HWHEADER_SIZE)
|
||||
|
||||
struct mvxpe_bm_chunk {
|
||||
struct mbuf *m; /* back pointer to mbuf header */
|
||||
void *sc; /* back pointer to softc */
|
||||
off_t off; /* offset of chunk */
|
||||
paddr_t pa; /* physical address of chunk */
|
||||
|
||||
off_t buf_off; /* offset of packet from sc_bm_buf */
|
||||
paddr_t buf_pa; /* physical address of packet */
|
||||
vaddr_t buf_va; /* virtual addres of packet */
|
||||
size_t buf_size; /* size of buffer (exclude hdr) */
|
||||
|
||||
LIST_ENTRY(mvxpe_bm_chunk) link;
|
||||
/* followed by packet buffer */
|
||||
};
|
||||
|
||||
struct mvxpe_bm_softc {
|
||||
bus_dma_tag_t bm_dmat;
|
||||
bus_dmamap_t bm_map;
|
||||
kmutex_t bm_mtx;
|
||||
|
||||
/* DMA MAP for entire buffer */
|
||||
char *bm_buf;
|
||||
|
||||
/* memory chunk properties */
|
||||
size_t bm_slotsize; /* size of bm_slots include header */
|
||||
size_t bm_chunk_count; /* number of chunks */
|
||||
size_t bm_chunk_size; /* size of packet buffer */
|
||||
off_t bm_chunk_header_size; /* size of hader + padding */
|
||||
off_t bm_chunk_packet_offset; /* allocate m_leading_space */
|
||||
struct mvxpe_bm_chunk *bm_slots[MVXPE_BM_SLOTS];
|
||||
|
||||
/* for software based management */
|
||||
LIST_HEAD(__mvxpe_bm_freehead, mvxpe_bm_chunk) bm_free;
|
||||
LIST_HEAD(__mvxpe_bm_inusehead, mvxpe_bm_chunk) bm_inuse;
|
||||
} sc_bm;
|
||||
|
||||
#define BM_SYNC_ALL 0
|
||||
|
||||
/*
|
||||
* Ethernet Device main context
|
||||
*/
|
||||
struct mvxpe_softc {
|
||||
device_t sc_dev;
|
||||
int sc_port;
|
||||
uint32_t sc_version;
|
||||
|
||||
/*
|
||||
* sc_mtx must be held by interface functions to/from
|
||||
* other frameworks. interrupt hander, sysctl hander,
|
||||
* ioctl hander, and so on.
|
||||
*/
|
||||
kmutex_t sc_mtx;
|
||||
|
||||
/*
|
||||
* Ethernet facilities
|
||||
*/
|
||||
struct ethercom sc_ethercom;
|
||||
struct mii_data sc_mii;
|
||||
u_int8_t sc_enaddr[ETHER_ADDR_LEN]; /* station addr */
|
||||
int sc_if_flags;
|
||||
int sc_wdogsoft;
|
||||
|
||||
/*
|
||||
* Configuration Parameters
|
||||
*/
|
||||
struct mvxpe_conf sc_cf;
|
||||
|
||||
/*
|
||||
* I/O Spaces
|
||||
*/
|
||||
bus_space_tag_t sc_iot;
|
||||
bus_space_handle_t sc_ioh; /* all registers handle */
|
||||
bus_space_handle_t sc_mibh; /* mib counter handle */
|
||||
|
||||
/*
|
||||
* DMA Spaces
|
||||
*/
|
||||
bus_dma_tag_t sc_dmat;
|
||||
struct mvxpe_rx_ring sc_rx_ring[MVXPE_QUEUE_SIZE];
|
||||
struct mvxpe_tx_ring sc_tx_ring[MVXPE_QUEUE_SIZE];
|
||||
int sc_tx_pending; /* total number of tx pkt */
|
||||
|
||||
/*
|
||||
* Software Buffer Manager
|
||||
* XXX: to be writtten the independent device driver.
|
||||
*/
|
||||
struct mvxpe_bm_softc sc_bm;
|
||||
|
||||
/*
|
||||
* Maintance clock
|
||||
*/
|
||||
callout_t sc_tick_ch; /* tick callout */
|
||||
|
||||
/*
|
||||
* Link State control
|
||||
*/
|
||||
uint32_t sc_linkstate;
|
||||
|
||||
/*
|
||||
* Act as Rndom source
|
||||
*/
|
||||
krndsource_t sc_rnd_source;
|
||||
|
||||
/*
|
||||
* Sysctl interfaces
|
||||
*/
|
||||
struct sysctllog *sc_mvxpe_clog;
|
||||
struct mvxpe_sysctl_queue sc_sysctl_rx_queue[MVXPE_QUEUE_SIZE];
|
||||
struct mvxpe_sysctl_queue sc_sysctl_tx_queue[MVXPE_QUEUE_SIZE];
|
||||
|
||||
/*
|
||||
* MIB counter
|
||||
*/
|
||||
size_t sc_sysctl_mib_size;
|
||||
struct mvxpe_sysctl_mib *sc_sysctl_mib;
|
||||
|
||||
#ifdef MVXPE_EVENT_COUNTERS
|
||||
/*
|
||||
* Event counter
|
||||
*/
|
||||
struct mvxpe_evcnt sc_ev;
|
||||
#endif
|
||||
};
|
||||
#define MVXPE_RX_RING_MEM_VA(sc, q) \
|
||||
((sc)->sc_rx_ring[(q)].rx_descriptors)
|
||||
#define MVXPE_RX_RING_MEM_PA(sc, q) \
|
||||
((sc)->sc_rx_ring[(q)].rx_descriptors_map->dm_segs[0].ds_addr)
|
||||
#define MVXPE_RX_RING_MEM_MAP(sc, q) \
|
||||
((sc)->sc_rx_ring[(q)].rx_descriptors_map)
|
||||
#define MVXPE_RX_RING(sc, q) \
|
||||
(&(sc)->sc_rx_ring[(q)])
|
||||
#define MVXPE_RX_HANDLE(sc, q, i) \
|
||||
(&(sc)->sc_rx_ring[(q)].rx_handle[(i)])
|
||||
#define MVXPE_RX_DESC(sc, q, i) \
|
||||
((sc)->sc_rx_ring[(q)].rx_handle[(i)].rxdesc_va)
|
||||
#define MVXPE_RX_DESC_OFF(sc, q, i) \
|
||||
((sc)->sc_rx_ring[(q)].rx_handle[(i)].rxdesc_off)
|
||||
#define MVXPE_RX_PKTBUF(sc, q, i) \
|
||||
((sc)->sc_rx_ring[(q)].rx_handle[(i)].chunk)
|
||||
|
||||
#define MVXPE_TX_RING_MEM_VA(sc, q) \
|
||||
((sc)->sc_tx_ring[(q)].tx_descriptors)
|
||||
#define MVXPE_TX_RING_MEM_PA(sc, q) \
|
||||
((sc)->sc_tx_ring[(q)].tx_descriptors_map->dm_segs[0].ds_addr)
|
||||
#define MVXPE_TX_RING_MEM_MAP(sc, q) \
|
||||
((sc)->sc_tx_ring[(q)].tx_descriptors_map)
|
||||
#define MVXPE_TX_RING(sc, q) \
|
||||
(&(sc)->sc_tx_ring[(q)])
|
||||
#define MVXPE_TX_HANDLE(sc, q, i) \
|
||||
(&(sc)->sc_tx_ring[(q)].tx_handle[(i)])
|
||||
#define MVXPE_TX_DESC(sc, q, i) \
|
||||
((sc)->sc_tx_ring[(q)].tx_handle[(i)].txdesc_va)
|
||||
#define MVXPE_TX_DESC_OFF(sc, q, i) \
|
||||
((sc)->sc_tx_ring[(q)].tx_handle[(i)].txdesc_off)
|
||||
#define MVXPE_TX_MBUF(sc, q, i) \
|
||||
((sc)->sc_tx_ring[(q)].tx_handle[(i)].txdesc_mbuf)
|
||||
#define MVXPE_TX_MAP(sc, q, i) \
|
||||
((sc)->sc_tx_ring[(q)].tx_handle[(i)].txdesc_mbuf_map)
|
||||
|
||||
#endif /* _IF_MVXPEVAR_H_ */
|
||||
Loading…
Reference in New Issue