5ee554064d
Reworked IRIX signal delivery so that ucontext is used instead of sigcontext
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when SA_SIGINFO is used. The IRIX process will hence find the expected
information using the third argument of the signal handler.
We do not provide code and siginfo yet.
2002-04-12 18:44:57 +00:00
9ca6637757
opt_footbridge.h no longer exists.
2002-04-12 18:01:17 +00:00
04d3df6513
Enable AGP GART support by default.
2002-04-12 17:58:17 +00:00
e588351a82
Don't need to install spkr.h
2002-04-12 13:33:23 +00:00
1283cdaaed
Add <luna68k/svr4_machdep.h>, since that seems to be necessary to get
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things to compile.
2002-04-12 12:46:39 +00:00
6e066ba77a
Add commented-out USERCONF option. Mainly useful for install media
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and can be optionally enabled based on miniroot and ramdisk size
requirements.
2002-04-12 08:10:45 +00:00
a6159879f0
Remove footbridge-specific stuff that will never apply on the Integrator.
2002-04-12 06:13:42 +00:00
dab39d6237
use ${ELF2ECOFF} from <bsd.{own,sys}.mk>
2002-04-12 05:11:17 +00:00
a7d9bc4bf3
Processing pending interrupts before reenabling external interrupts in splx().
2002-04-12 04:52:57 +00:00
b5ee40947f
Disable TXFIFO on npwr. There is some sort of serial interrupt lossage that
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seems to be greatly alleviated by this change.
2002-04-12 03:01:57 +00:00
8989cea6a8
Enable pciide, wd, atapibus, and atapi devices.
2002-04-12 02:57:00 +00:00
b5b11bf5f5
Map winbond interrupts.
2002-04-12 02:55:03 +00:00
67dbc34547
Remove exception for CONSPEED on NPWR -- current redboot uses 115200, too.
2002-04-12 00:58:49 +00:00
49df0c927f
Lose -nbsd
2002-04-11 21:47:36 +00:00
3a33a1deec
Jason claims that nothing tests for RISCPC any more. Make it so.
2002-04-11 17:31:23 +00:00
ac60400580
The results of my cats NWDO hacking.
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This was tested using a custom INSTALL kernel. The current one is >4Mb
which the cats firmware can't currently boot. We need to decide what
needs to be removed from INSTALL.
2002-04-11 16:33:58 +00:00
b7cae9b821
Pass fully encoded bus addresses in the attach arguments.
2002-04-11 11:11:23 +00:00
24db2d2924
pmap_kremove4_4c(): correctly compute the maximum number of pages to be
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unmapped within a segment.
2002-04-11 11:08:40 +00:00
de43efffee
G/c non-netwinder stuff.
2002-04-10 22:35:17 +00:00
bfe71d0a4b
vm_offset_t -> vaddr_t,paddr_t
2002-04-10 22:30:44 +00:00
27d98ca694
Remove the Control register handling from arm32_vector_init(). Apparently,
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the ARM6 and ARM7 do completely the wrong thing if you read this register,
so we have to handle this a different way.
2002-04-10 21:45:43 +00:00
d2a6d9baa7
Remove obsolete tests of "netwinder" and "footbridge".
2002-04-10 20:30:30 +00:00
2bbba08b60
Delete option SAIP; nothing tests it.
2002-04-10 20:20:04 +00:00
9d1c2c73c1
Eliminate all #ifdef HPCARM, and delete the option.
2002-04-10 20:17:23 +00:00
e52d5c4ec1
Remove FOOTBRIDGE.
2002-04-10 20:13:54 +00:00
4a45f1922b
Remove meaningless test against FOOTBRIDGE.
2002-04-10 20:13:20 +00:00
4f778bc49c
G/c FOOTBRIDGE option.
2002-04-10 20:12:08 +00:00
a9242efbfb
Remove options NETWINDER and FOOTBRIDGE; nothing tests for them.
2002-04-10 20:11:44 +00:00
59d47eeb79
Remove "options RISCPC"; nothing tests for it anymore.
2002-04-10 20:10:08 +00:00
59c9e94b72
vm_offset_t -> vaddr_t,paddr_t
2002-04-10 19:35:22 +00:00
d5ecd48d67
DTRT to avoid installing "netbsd.tmp" in /usr/mdec.
...
Addresses port-mvme68k/16282.
2002-04-10 18:43:21 +00:00
ad2350dccf
On XScale processors where we use write-back caching, use are
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read/write-allocate line allocation policy.
On the i80321, this improves nearly every lmbench benchmark, dramatically
so the ones that are sensitive to memory bandwidth (100-300% improvement
for these).
2002-04-10 17:39:31 +00:00
2b924304ab
Add a new function, pmap_alloc_ptpt(), that allocates the PTPT and
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maps it the way we want, rather than using uvm_km_zalloc() and playing
the "revoke cacheability" song-and-dance.
2002-04-10 17:08:13 +00:00
cad393fa1c
pmap_alloc_l1pt(): Just enter the mappings for the L1 table by
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hand, rather than calling pmap_kenter_pa() and then revoking
cacheability in the PTE.
2002-04-10 15:56:21 +00:00
cd0e28f1e7
Use L2_S_CACHE_MASK in places where we revoke cacheability.
2002-04-10 15:44:23 +00:00
4fb4a95b7e
Install cpu.h. Noted in PR port-powerpc/16285 from smi@sm.sony.co.jp.
2002-04-10 15:36:42 +00:00
937863b61e
Add (missing) scsibus* at adw?
2002-04-10 13:41:04 +00:00
2b96151049
Disable BOOT_AOUT.
2002-04-10 13:38:42 +00:00
cc2da29e03
Correct an error message.
2002-04-10 10:09:31 +00:00
41ec4fe6c2
Accept the bus_dma_tag_t for obio, too.
2002-04-10 05:13:09 +00:00
668547d841
pmap_kenter_pa(): Obey the "prot" argument, rather than simply making
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all mappings r/w (!!).
2002-04-10 04:40:58 +00:00
648cd86d69
Use m68k/m68k/cacheops.[ch]
...
Use m68k/m68k/bus_dma.c
- Add mainbus_attach_args with bus_space_tag_t and bus_dma_tag_t.
- Use passed-in tags for nubus scan.
2002-04-10 04:38:48 +00:00
0844eedc55
bus_dma(9) pulled pretty much verbatim from next68k.
2002-04-10 04:36:20 +00:00
15aef6da21
Oops; fix the second usage.
2002-04-10 04:19:47 +00:00
9502007faf
osf1_errno_rxlist[] -> native_to_osf1_errno[]
2002-04-10 04:18:31 +00:00
6e52cbf89e
In pmap_copy_page_xscale(), put the source page in the mini-data
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cache, as well. The mini-data cache is 2-way, so src and dst won't
clobber each other, and the smallness of the cache doesn't matter,
since we access each page once sequentially.
While we still have to do the initial clean of the source page, this
saves another 4K of main D$ pollution, and also means we don't have
to do 2 cache passes after the copy is complete (i.e. we can skip the
invalidation of the source page in the main cache, since it's no longer
there).
2002-04-10 01:30:42 +00:00
2092e78cec
Add separate pmap_{zero,copy}_page() functions for generic ARM
...
vs. XScale. Use the mini-data cache for the destination on XScale,
thus saving tossing out 4K of possible-useful data from the main
data cache each time.
This significantly improves every test in lmbench.
2002-04-10 00:45:43 +00:00
da162bee90
* Move the code that cleans the XScale mini-data cache into its
...
own function.
* Add a new function which sets up the mini-data cache clean area
properly.
2002-04-09 23:44:00 +00:00
1b20a04772
* Split pte_cache_mode into pte_l1_s_cache_mode, pte_l2_l_cache_mode,
...
and pte_l2_s_cache_mode. The cache-meaningful bits are different
for these descriptor types on some processor models.
* Add pte_*_cache_mask, corresponding to each above, which has a mask
of the cache-meangful bits, and define those for generic and XScale
MMU classes. Note, the L2_S_CACHE_MASK_xscale definition requires
use of the Extended Small Page L2 descriptor (the "X" bit overlaps
with AP bits otherwise).
2002-04-09 22:37:00 +00:00
de29118bc5
Use the "Extended Small Page" L2 descriptor type on XScale (note
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this means that there are no 1K sub-pages on XScale, but we don't
use them anyway).
2002-04-09 21:23:16 +00:00
manu