Commit Graph

700 Commits

Author SHA1 Message Date
matt
549ac19770 Add IBM Power3 CPUID. 2002-08-10 21:38:06 +00:00
matt
67f40b1907 More refinement, only map B_READ buf with VM_PROT_WRITE (all pages always
have VM_PROT_READ).  Also, pass PMAP_WIRED to pmap_enter (for non-mpc6xx
pmaps).  This will give pmap clues about flushing any "icache ok state".
2002-08-10 18:49:56 +00:00
matt
246ee3ef1d Switch vmap*buf back to using pmap_enter/pmap_remove. This is so that
accesses to the buffer will cause the reference and modified bits for
the pages to be udpated appropriately.
2002-08-10 16:28:49 +00:00
simonb
5b415a20e5 Fix for when EMAC_EVENT_COUNTERS isn't defined. Problem reported by
Allen Briggs.
2002-08-09 14:10:30 +00:00
simonb
acce3a5e36 Add a driver the for IBM 405gp (and possibly other IBM 4xx cpus) ethernet
MAC (emac).  Much thanks to Jason Thorpe for debugging help writing this
driver.  Tested on the walnut, and an earlier version of this driver works
on the OpenBlockSS.
2002-08-09 04:17:26 +00:00
matt
0fb9cba190 Add SPR_ASR from OEA-64. Change mfspr to use register_t. 2002-08-08 22:49:09 +00:00
chs
0a97a311e2 it's PPC_HAVE_FPU, not PPC_HAS_FPU.
also, include the headers that turn on FPU and AltiVec features
in case no one else does.
2002-08-08 01:27:35 +00:00
matt
e66a17771e Disable PTE_EXEC optimization until I figure out why it fails on 750 but
not 74xx.
2002-08-07 19:04:05 +00:00
tsubai
e373d8b520 Re-correct previous. It's intentional. 2002-08-07 08:01:57 +00:00
briggs
0b956d0b8b Implement pmc(9) -- An interface to hardware performance monitoring
counters.  These counters do not exist on all CPUs, but where they
do exist, can be used for counting events such as dcache misses that
would otherwise be difficult or impossible to instrument by code
inspection or hardware simulation.

pmc(9) is meant to be a general interface.  Initially, the Intel XScale
counters are the only ones supported.
2002-08-07 05:14:47 +00:00
matt
a2e9fe106d Correct __va_list typedef for GCC 3.* to match the GCC 3.* definition. 2002-08-07 00:11:59 +00:00
chs
f7fb853264 be sure to re-enable interrupts before calling trap() a second time
due to an AST.  the rule is that we must always have interrupts
enabled when acquiring kernel_lock, so that we can process blocking IPIs
from another CPU which is already holding kernel_lock.
reduce differences between the MP and non-MP versions of this file.
2002-08-06 06:21:58 +00:00
chs
f73abf90fb on MP systems, if the firmware didn't configure the L2 cache
on the non-boot CPUs, copy the L2CR configuration from the boot CPU.
also, fix the code that configures the L2 cache so that it works at all.
while I'm here, use mfspr() and mtspr() instead of inline asms.
2002-08-06 06:20:08 +00:00
chs
2928d8ba05 actually we shouldn't hold kernel_lock while calling postsig(). 2002-08-06 06:18:24 +00:00
chs
0924752f24 add the MSSCR0 register and some more L2CR fields. 2002-08-06 06:17:50 +00:00
chs
461184c6b6 fix the calculation of the address of the IPI dispatch register. 2002-08-06 06:16:42 +00:00
chs
301f1ebf31 move more inlines to cpu.h: mftb(), mftbl() and mfpvr().
(the mftb() in pmap.c only wanted the lower 32 bits, so that's now mftbl()).
2002-08-06 06:14:33 +00:00
enami
a55bfb4d51 A cosmetic change. 2002-08-05 02:56:58 +00:00
enami
1aaddc3669 - Care about carry bit when adding short value to force 4 byte boundary.
It may contain any 32 bit value there.
- Use correct instruction to clear carry bit.
- Don't use series of load with update instruction.  It's slower.
2002-08-05 02:55:39 +00:00
simonb
7cfa7d3ce0 Sprinkle a small amount of KNF. 2002-08-03 13:12:44 +00:00
chs
810cde53cc use a completely separate trap handler for syscall traps.
this reduces syscall overhead by 10% to 20% depending on cpu type.
2002-08-02 03:46:42 +00:00
simonb
d16ca1844f Add driver for 405gp (and other 4xx?) watchdog timer. 2002-08-01 23:15:37 +00:00
matt
3e158de7c1 Don't define register references if not KERNEL or STANDALONE. 2002-07-30 06:09:10 +00:00
itojun
f8e5e9c295 be friendly with gcc-3.1.1 -O2, which takes advantage of ANSI C
pointer aliasing rule (gcc optimization/7427).  from tsubai, sync w/kame
2002-07-29 09:14:36 +00:00
chs
03315186b6 install atomic.h. 2002-07-28 07:11:25 +00:00
chs
a7171ee431 add some atomic operations. 2002-07-28 07:09:28 +00:00
chs
fccc379b30 restructure the FPU and AltiVEC code so that it works for MP. 2002-07-28 07:07:44 +00:00
chs
64094057a1 resync the MP and non-MP trap_subr's. 2002-07-28 07:06:27 +00:00
chs
a7763f6e2c create a syscall_plain() like on other platforms
and avoid getting the kernel lock for MPSAFE syscalls.
2002-07-28 07:05:53 +00:00
chs
0e5816fca3 remove a local copy of mfmsr(). 2002-07-28 07:05:19 +00:00
chs
7f81a49168 propagate the MP idle-loop fix to ppc from the other ports:
Move call to sched_unlock_idle to later in the context switch to
  eliminate a race where another processor could grab the outgoing
  process before we were done saving our state into it, with predictable
  results.

  Bug spotted by Frank van der Linden <fvdl@wasabisystems.com>

also, don't re-enable interrupts temporarily in the middle of
switching to a new process, just wait until we're completely switched.
this didn't work on MP and it's not worth the effort.
2002-07-28 07:05:06 +00:00
chs
badae2dc11 disable the PTE_EXEC optimization for MP for now.
PTE_EXEC needs to become a per-CPU flag eventually.
2002-07-28 07:03:47 +00:00
chs
9b01e8d8ce split off the part of cpu_attach_common() that pokes at special CPU registers
into a separate function so that we can run it on each CPU we configure
rather than always on the boot CPU.
2002-07-28 07:03:15 +00:00
chs
84b41b2adb rearrange the PCB structure a bit so it's easier to look at in ddb. 2002-07-28 07:02:54 +00:00
chs
4b5a2a3f79 define CPU_INFO iterators so that the CPU-states sysctl works for MP. 2002-07-28 07:02:29 +00:00
matt
f9be6bb495 Cleanup AltiVec data stream issues with context switching. Don't stop
data streams on execptions/interrupts since the processor will suspend
them for us.  Only stop them on 1) process exit, 2) another process gets
its address space loaded, and 3) (for completeness only) we save a process's
AltiVec context.
2002-07-25 23:46:47 +00:00
matt
a660a9325f Set normal memory PTEs with PTE_M (memory coherent). Change how we
remember the "exec"ness of a page.  If a managed page is pmap_enter'ed
with VM_PROT_EXECUTE, remember that it's an "exec"page.  Such that when
additional mapping are performed, no synch'ing of the I-cache is needed.
Revoke "exec"ness when the page is mapped into the kernel with VM_PROT_WRITE
or the pmap_page_protect is called with VM_PROT_NONE.
2002-07-25 23:33:04 +00:00
chs
4e9f286b98 for MP builds, save and restore sprg0 (which contains the curcpu pointer)
around restoring OFW's sprg registers while calling into OFW.
2002-07-24 06:04:43 +00:00
chs
185a5bbcf0 rename the intr_depth field of struct intrframe to avoid a name conflict
in MULTIPROCESSOR builds.
2002-07-24 05:44:37 +00:00
chs
804e68d33a reimplement copy{in,out}str() similarly to copy{in,out}()
(instead of the old way of calling [fs]ubyte() in a loop).
2002-07-24 04:59:32 +00:00
matt
cde20d8743 Make sure that pmap_zero_page and pmap_copy_page don't make calls or
reference while relocation is disabled since the stack will be inaccessible.
Add support for using AltiVec in pmap_zero_page and pmap_copy_page on
AltiVec capable processors.
2002-07-18 22:51:57 +00:00
matt
436f257283 Add a common file to do pmap_zero_page/pmap_copy_page/pmap_pageidlezero and
pmap_syncicache.  This file uses a ppc feature in a sick and twisted way
to avoid mapping the physical pages used by those routines.  It performs
the operations with the MMU disabled but PPC exception save and retstore
the machine state and are invoked with the MMU disabled, this doesn't have
an adverse effect on the system.

Currently only enable for MPC6xx and !OLDPMAP.
2002-07-17 03:11:07 +00:00
matt
ece8b74130 Add machdep.powerpc sysctl. Change the default value of powersave to -1
(< 0 mean no powersave available).  Enable powersave by default for
750/7400/7410 but leave if off for 7450/7455.
2002-07-16 23:04:20 +00:00
matt
3dc1994d70 Don't install extintr handler if not supplied.
Make panic message more informative.
2002-07-16 16:39:12 +00:00
matt
b35e786de2 Add a linux_syscall_intern entry (appropriately ifdef'ed COMPAT_LINUX).
When/if PPC ever supports LKMs, this should be moved to a separate file.
2002-07-11 19:32:43 +00:00
simonb
873edaed34 Clean up some white space niggles. 2002-07-11 01:38:48 +00:00
matt
6e81c6293f Bump VM kernel buffer space from 128MB to 192MB now that we have 512MB of
KVA space.
2002-07-10 05:25:12 +00:00
matt
7c3dbdc01d When allocate VA for the msgbuf, don't allocate pages too since we have
already done that in pmap_bootstrap.  (fixes a small page leak at startup).
2002-07-09 19:05:00 +00:00
matt
e64bc5acc1 Allow USER_SR to be overriden on a per-port basis 2002-07-07 19:29:18 +00:00
matt
140a273f7a Use lvewx/stvewx for VSCR and save ourselves 12 bytes we don't need to load. 2002-07-07 00:46:20 +00:00