Commit Graph

10652 Commits

Author SHA1 Message Date
pk 9ceaaf3e7b Turn off "cache pagetables bit" on non-MXCC modules. 1997-03-12 22:52:19 +00:00
mycroft b8d7e3deab No longer needed. 1997-03-12 22:40:07 +00:00
cgd 2330e40bc9 enable Matt Jacob's ISP 10x0 driver, now that it's in the source tree. 1997-03-12 21:50:15 +00:00
cgd 8c689e6477 Copyright notice consistency, per Matthew Jacob. 1997-03-12 21:09:43 +00:00
cgd cf26d31ad2 NetBSD RCS ID tweaks, a few comment block tweaks. Also, make copyright
notices consistent (per Matt Jacob).
1997-03-12 21:06:41 +00:00
cgd 099e30a322 ISP 10x0 driver from Matthew Jacob of NASA Ames Research Center.
(March 12, 1997 version).
1997-03-12 20:44:50 +00:00
fvdl 7fb73fe0b2 Fix error in computation of BSS size when clearing it. 1997-03-12 19:49:11 +00:00
ragge 2bbaeef8cc Fast and dirty fix to avoid panics during autoconf of KFQSA DSSI disks.
Controller errors showing up can't be handled anyway.
1997-03-12 19:42:30 +00:00
cgd 0daaaa0fc2 add kn8ae CPU support to GENERIC kernels. Also, add kn8ae devices.
Add "isp", "ahc", and "bha" config lines, but comment them out until
their sources are in the tree and/or their alpha patches are in the tree.
1997-03-12 19:29:14 +00:00
cgd ffba332bb5 AlphaServer 8200 & 8400 support, including CPU specific details, TurboLaser
system bus support, and KFTxx support.  From Matthew Jacob, NASA Ames
Research Center.
1997-03-12 19:19:54 +00:00
cgd 265be6d839 enabled SQWE as well as PIE in reg B. 1997-03-12 19:13:20 +00:00
thorpej a92ec8002e Enable COMPAT_M68K4K. 1997-03-12 18:33:09 +00:00
pk 8e4a126035 Use `mcxx' from cpuinfo instead of re-consulting the MMU registers 1997-03-12 15:44:28 +00:00
christos 0d71b22d50 Use genassym.cf 1997-03-12 15:17:13 +00:00
christos 3e35754576 Added genassym.cf 1997-03-12 15:16:35 +00:00
pk 6e3c9f3b59 Make sure to disable interrupts in the Interrupt Enable register as soon
as we've mapped it.
1997-03-12 11:04:35 +00:00
pk b197276005 Correct output from cpumatch_unknown() and add missing viking variant
to cpu table (noticed by Andrew Gillham).
1997-03-12 09:08:29 +00:00
cgd a0d3809966 specs for ISP 10x0 (isp) driver Sbus attachment. From Matt Jacob. 1997-03-12 06:43:25 +00:00
cgd 28152db63a don't assume that CPU ID is same as device unit number (DUH!), add some
comments about future work to be done.  make a mostly-extraneous set of
printfs (cpu capabilities) become #ifdef DEBUG.
1997-03-12 05:50:00 +00:00
cgd 245b65b853 pass CPU ID info down to cpu when attaching (duh!) 1997-03-12 05:47:37 +00:00
cgd 0a500fffa0 update to allow PCI bus interfaces that wish to allocate static
extent storage per interface unit (e.g. dwlpx, where there can be multiple
units per machine) to do so.  Inspired by discussion with and changes from
Matt Jacob.
1997-03-12 05:24:23 +00:00
cgd 55f902601c Set the halt flags in the right per-cpu-slot structure. From Matt Jacob. 1997-03-12 04:45:41 +00:00
cgd adad00a33a sanity check rpb_primary_cpu_id 1997-03-12 04:42:22 +00:00
cgd e4307285ba from Matt Jacob: deal with type 5 (passive release?) interrupts. (ignore them
but print out their vector(?) to see if we can ever discern anything useful
from it.)  Also, some slight general cleanup.
1997-03-12 04:22:30 +00:00
thorpej 1777807068 Add 9660 file system, and set DDB_ONPANIC to 0. 1997-03-12 02:08:02 +00:00
cgd 9a36b46f7a tlsb bus and device file specs, s/21000/kn8ae. From Matt Jacob. 1997-03-12 01:54:23 +00:00
cgd 7e33512f13 fix up kn8ae/DEC_21000 entry 1997-03-12 01:47:46 +00:00
gwr a9bc70551a Clarify duties of traps 1, 2, 12, 15 for emulations
Include <m68k/m68k/sigreturn.s> code.
Add/fix some comments...
1997-03-11 22:58:57 +00:00
gwr 4756c63625 Call isr_soft_request() at most once per zshard interrupt.
In the softintr, raise to spltty before calling tty code.
1997-03-11 21:54:35 +00:00
gwr 05a47d22ea Correct handling for Trap #2 in SunOS executables,
now that we know it is supposed to flush the cache.
(Was thought to be "some obscure FPU operation".)
1997-03-11 21:30:51 +00:00
gwr f64034e8f6 Sync up with changes in GENERIC 1997-03-11 21:21:49 +00:00
gwr b4de41ef34 Update the description of the flags for "si" devices.
Remove wired-down scsi disk targets (no longer needed).
Add ch, ss, uk (scsi devcies) at mycroft's requst.
1997-03-11 20:59:10 +00:00
gwr 3aa49c4b33 Remove unnecessary differences (T_BRKPT, T_WATCHPOINT gone). 1997-03-11 20:31:20 +00:00
gwr ec6bb1d018 s/-T/-Ttext/ 1997-03-11 20:13:20 +00:00
gwr 4ad7ed0b97 Moved dev_net.[ch] to sys/lib/libsa 1997-03-11 18:29:30 +00:00
sommerfe 9460da5eb9 Implement trace/t ("thread" trace) allowing traceback by process-id
rather than by frame pointer (which it a bit harder to find).
1997-03-11 16:38:23 +00:00
pk 92d853e309 4m memory fault traps: simplify fault address logic, since per-CPU
fault-status reading stubs pre-cook the arguments.

illegal instruction trap: catch iflush instructions that cause this trap
on some CPU/MMU combinations.
1997-03-11 01:20:25 +00:00
pk 01e424f233 Insert RCS Id. 1997-03-11 01:03:07 +00:00
pk abc39039f1 Move some parts of CP detection to cpu_attach() in cpu.c.
Call get_cpuinfo() for the boot CPU to collect the minimum information
to get the bootstrap rolling.
sun4/sun4c: the Interrupt Enable register is now mapped here after pmap
is initialized (was in locore).
Replace `cpumod' and `mmumod' with `cpuinfo.*' equivalents.
Allow more than one CPU to be configured in mainbus_attach().
1997-03-11 01:01:59 +00:00
pk 476ef3b431 Per-CPU information which is collected in cpu_attach().
Many things in here were imported from an earlier version from Aaron
Brown and are not yet used. This version has all the attributes of a
snapshot; more to come as addtional CPU/MMU details get implemented.
1997-03-11 00:55:24 +00:00
pk eb71a02a7f Re-write of CPU/MMU detection code.
Use a table driven classification based on CPU and MMU implementation/version
fields. Each CPU class or module defines a collection of routines that
implement CPU or MMU specific operations that can collect detailed setup
information.

All information is collected in a `cpu_softc' structure provided by the
auto-configuration code. However, in the interest of SMP support this
structure is located at a fixed virtual address identified by the
symbol `cpuinfo'. The `boot' CPU currently uses the the physical page(s) at
address 0x2000 for its cpuinfo. Consequently, the fixed virtual address
will be `KERNBASE+0x2000'.

The cache flush routines for several systems (sun4/4c vs. sun4m;
virtual vs. physical tags) have been factored out. Function pointers
to an appropriate set are located in `cpuinfo'. The former global
`cacheinfo' structure is now also a part of `cpuinfo'. Because of the
fixed virtual address of `cpuinfo' no extra performance penalties
are incurred by this move. In multi-architecture kernels, there's
no longer the need for run-time `cputyp' tests in this part of the system.
1997-03-11 00:44:00 +00:00
pk 8d2c03c810 Replace `cputyp' run-time tests by inserting multiple branches and NOPing
some at startup depending on architecture.

Use `get_faultstatus' field in `cpuinfo' (initialized in cpu.c) to branch
to CPU/MMU specific fault status reading stubs on memory fault traps.

Remove code top map the Interrupt Enable register on sun4/sun4c. Its VA
has moved to a high location and is now mapped in autoconf.c after
pmap has initialized. Note: this renders NMIs during bootstrap() fatal
(maybe loading %tbr should be deferred).
1997-03-11 00:09:29 +00:00
pk 7d6231865e Use cache flush routines provided in `cpuinfo'. 1997-03-10 23:55:40 +00:00
pk 129d9d5cf6 Move VA of the sun4/sun4c Interrupt Enable register from locore.
Define VA for the per-CPU `cpuinfo' structure.
1997-03-10 23:54:41 +00:00
pk a566decb35 Use many things from the newly defined `cpuinfo' structure:
- vcache_flush_*() routines.
	- cpu_type/cpu_flags
	- per cpu context table and context administration glue.
	- different macros to enable sun4/3-level mmu support.

Simplify sun4m version of pmap_bootstrap() a bit; more to do still.

Move installation of page tables in MMU into a separate routine, in
anticipation for SMP.
1997-03-10 23:26:11 +00:00
pk ca1c4cc6c3 Define CPUINFO_FAULTSTATUS for use in locore.s 1997-03-10 23:15:03 +00:00
pk 4f30101165 Leave `has_iocache' unset if cache not enabled. 1997-03-10 23:13:59 +00:00
pk 593dbcc7dd Replace `cpumod' with `cpuinfo.cpu_type' equivalent. 1997-03-10 23:09:55 +00:00
pk d1be7c7ea4 New location of Interrupt Enable register on sun4/sun4c. 1997-03-10 23:08:31 +00:00
pk d8fc2afd1e Replace `cpumod' with `cpuinfo.cpu_type' equivalents. 1997-03-10 23:01:40 +00:00