4m memory fault traps: simplify fault address logic, since per-CPU
fault-status reading stubs pre-cook the arguments. illegal instruction trap: catch iflush instructions that cause this trap on some CPU/MMU combinations.
This commit is contained in:
pk
parent
01e424f233
commit
92d853e309
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@ -1,4 +1,4 @@
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/* $NetBSD: trap.c,v 1.50 1996/12/01 23:21:07 pk Exp $ */
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/* $NetBSD: trap.c,v 1.51 1997/03/11 01:20:25 pk Exp $ */
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/*
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* Copyright (c) 1996
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@ -84,6 +84,7 @@
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#include <sparc/fpu/fpu_extern.h>
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#include <sparc/sparc/memreg.h>
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#include <sparc/sparc/cpuvar.h>
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#define offsetof(s, f) ((int)&((s *)0)->f)
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@ -190,6 +191,8 @@ static int fixalign __P((struct proc *, struct trapframe *));
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void mem_access_fault __P((unsigned, int, u_int, int, int, struct trapframe *));
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void mem_access_fault4m __P((unsigned, u_int, u_int, u_int, u_int, struct trapframe *));
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void syscall __P((register_t, struct trapframe *, register_t));
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int trap_instr __P((int, struct trapframe *));
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static int decode_address __P((int, struct trapframe *));
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/*
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* Define the code needed before returning to user mode, for
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@ -241,6 +244,68 @@ userret(p, pc, oticks)
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curpriority = p->p_priority;
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}
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/*
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* Decode a trapped instruction to see if we should do
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* something about it.
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*/
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int
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trap_instr(pc, tf)
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register int pc;
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register struct trapframe *tf;
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{
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union instr instr;
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if (copyin((caddr_t)pc, &instr, sizeof(instr)) != 0)
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return(0);
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if (instr.i_any.i_op == 2 &&
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instr.i_op3.i_op3 == IOP3_FLUSH) {
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int addr = decode_address(instr.i_int, tf);
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cpuinfo.cache_flush((caddr_t)addr, 4); /*XXX*/
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return(1);
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}
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return(0);
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}
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/*
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* Get source address from an `op3' instruction.
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*/
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static int
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decode_address(instruction, tf)
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int instruction;
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struct trapframe *tf;
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{
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union instr instr;
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int addr, i, rs[2], offset;
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instr.i_int = instruction;
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rs[0] = instr.i_op3.i_rs1;
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i = instr.i_simm13.i_i;
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if (i) {
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rs[1] = 0;
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offset = instr.i_simm13.i_simm13;
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} else {
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rs[1] = instr.i_op3.i_low14 & 0x1f;
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offset = 0;
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}
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for (addr = 0, i = 0; i < 2; i++) {
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int r = rs[i];
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if (r < 16) {
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addr += r == 0 ? 0 : tf->tf_global[r];
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} else {
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struct rwindow rwindow;
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write_user_windows();
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/* Copy frame from user stack */
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if (copyin((caddr_t)tf->tf_out[6],
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&rwindow, sizeof(rwindow)) != 0)
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return (-1);
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addr += rwindow.rw_local[r];
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}
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}
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return (addr + offset);
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}
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/*
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* If someone stole the FPU while we were away, do not enable it
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* on return. This is not done in userret() above as it must follow
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@ -309,7 +374,12 @@ trap(type, psr, pc, tf)
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ADVANCE;
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return;
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}
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goto dopanic;
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dopanic:
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printf("trap type 0x%x: pc=%x npc=%x psr=%s\n",
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type, pc, tf->tf_npc, bitmask_snprintf(psr,
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PSR_BITS, bits, sizeof(bits)));
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panic(type < N_TRAP_TYPES ? trap_type[type] : T);
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/* NOTREACHED */
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}
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if ((p = curproc) == NULL)
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p = &proc0;
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@ -321,12 +391,15 @@ trap(type, psr, pc, tf)
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default:
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if (type < 0x80) {
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dopanic:
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#ifdef SUSTAIN_BOGUS_TRAPS
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if (0)
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#endif
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goto dopanic;
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printf("trap type 0x%x: pc=%x npc=%x psr=%s\n",
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type, pc, tf->tf_npc, bitmask_snprintf(psr,
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PSR_BITS, bits, sizeof(bits)));
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panic(type < N_TRAP_TYPES ? trap_type[type] : T);
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/* NOTREACHED */
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trapsignal(p, SIGILL, type);
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break;
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}
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#if defined(COMPAT_SVR4)
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badtrap:
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@ -355,6 +428,10 @@ badtrap:
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break; /* the work is all in userret() */
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case T_ILLINST:
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if (trap_instr(pc, tf)) {
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ADVANCE;
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break;
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}
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trapsignal(p, SIGILL, 0); /* XXX code?? */
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break;
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@ -789,9 +866,6 @@ mem_access_fault4m(type, sfsr, sfva, afsr, afva, tf)
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int onfault;
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u_quad_t sticks;
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char bits[64];
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#if DEBUG
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static int lastdouble;
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#endif
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cnt.v_trap++;
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if ((p = curproc) == NULL) /* safety check */
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@ -818,7 +892,7 @@ static int lastdouble;
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memerr4m(type, sfsr, sfva, afsr, afva, tf);
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/*
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* If we get here, exit the trap handler and wait for the
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* trap to reoccur
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* trap to re-occur.
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*/
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goto out;
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}
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@ -848,26 +922,12 @@ static int lastdouble;
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goto out; /* No fault. Why were we called? */
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/*
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* This next section is a mess since some chips use sfva, and others
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* don't on text faults. We want to use sfva where possible, since
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* we _could_ be dealing with an ASI 0x8,0x9 data access to text space,
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* which would trap as a text fault, at least on a HyperSPARC. Ugh.
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* XXX: Find out about MicroSPARCs.
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* NOTE: the per-CPU fault status register readers (in locore)
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* may already have decided to pass `pc' in `sfva', so we avoid
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* testing CPU types here.
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* Q: test SFSR_FAV in the locore stubs too?
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*/
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if (type == T_TEXTFAULT && mmumod == SUN4M_MMU_SS &&
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(cpumod & 0xf0) == (SUN4M_SS) && (sfsr & SFSR_FAV)) {
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sfva = pc; /* can't trust fav on supersparc/text fault */
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} else if (type == T_TEXTFAULT && mmumod != SUN4M_MMU_HS) {
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sfva = pc;
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} else if (!(sfsr & SFSR_FAV)) {
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#ifdef DEBUG
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if (type != T_TEXTFAULT)
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printf("mem_access_fault: got fault without valid SFVA\n");
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if (mmumod == SUN4M_MMU_HS)
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printf("mem_access_fault: got fault without valid SFVA on "
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"HyperSPARC!\n");
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#endif
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if ((sfsr & SFSR_FAV) == 0) {
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if (type == T_TEXTFAULT)
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sfva = pc;
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else
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@ -876,7 +936,7 @@ static int lastdouble;
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if ((sfsr & SFSR_FT) == SFSR_FT_TRANSERR) {
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/* Translation errors are always fatal, as they indicate
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* a corrupt translation (page) table heirarchy.
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* a corrupt translation (page) table hierarchy.
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*/
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if (tfaultaddr == sfva) /* Prevent infinite loops w/a static */
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goto fault;
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@ -889,41 +949,17 @@ static int lastdouble;
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va = trunc_page(sfva);
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#ifdef DEBUG
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if (lastdouble) {
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printf("stacked tfault @ %x (pc %x); sfsr %x", sfva, pc, sfsr);
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lastdouble = 0;
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if (curproc == NULL)
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printf("NULL proc\n");
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else
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printf("pid %d(%s); sigmask %x, sigcatch %x\n",
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curproc->p_pid, curproc->p_comm,
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curproc->p_sigmask, curproc->p_sigcatch);
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}
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#endif
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if (((sfsr & SFSR_AT_TEXT) || type == T_TEXTFAULT) &&
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!(sfsr & SFSR_AT_STORE) && (sfsr & SFSR_OW)) {
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if (psr & PSR_PS) /* never allow in kernel */
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goto kfault;
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#if 0
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/*
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* Double text fault. The evil "case 5" from the HS manual...
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* Attempt to handle early fault. Ignores ASI 8,9 issue...may
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* do a useless VM read.
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* XXX: Is this really necessary?
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*/
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#ifdef DEBUG
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if (dfdebug) {
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lastdouble = 1;
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printf("mem_access_fault: double text fault @ %x (pc %x); sfsr %x",
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sfva, pc, sfsr);
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if (curproc == NULL)
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printf("NULL proc\n");
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else
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printf(" pid %d(%s); sigmask %x, sigcatch %x\n",
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curproc->p_pid, curproc->p_comm,
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curproc->p_sigmask, curproc->p_sigcatch);
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}
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#endif
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if (mmumod == SUN4M_MMU_HS) { /* On HS, we have va for both */
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if (vm_fault(kernel_map, trunc_page(pc),
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VM_PROT_READ, 0) != KERN_SUCCESS)
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@ -933,6 +969,7 @@ static int lastdouble;
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#endif
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;
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}
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#endif
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}
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/* Now munch on protections... */
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@ -980,7 +1017,7 @@ static int lastdouble;
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rv = mmu_pagein4m(&vm->vm_pmap, va,
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sfsr & SFSR_AT_STORE ? VM_PROT_WRITE : VM_PROT_READ);
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if (rv < 0)
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printf(" sfsr=%x(FT=%x,AT=%x,LVL=%x), sfva=%x, pc=%x, psr=%x\n",
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uprintf(" sfsr=%x(FT=%x,AT=%x,LVL=%x), sfva=%x, pc=%x, psr=%x\n",
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sfsr, (sfsr >> 2) & 7, (sfsr >> 5) & 7, (sfsr >> 8) & 3,
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sfva, pc, psr);
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if (rv > 0)
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