Commit Graph

446 Commits

Author SHA1 Message Date
matt
44003b5fca The FP exception mode bits from the MSR will be stored in pcb_flags. From
there, they will copied to MSR as needed (when FP is enabled).  They will be
cleared from the MSR when the lwp loses the FPU.  Hence they need to be stored
someplace else.
2004-04-04 17:01:44 +00:00
matt
c0dce2fdd9 Be a lot more explicit about the MSR bits a user process can change. 2004-04-04 16:49:12 +00:00
matt
0d6bda4d21 When returning back to user mode, if the lwp has lost the FPU, not only
clear PSL_FP bit (to force a FPU Unavailable exception) but clear
PSL_FE0 and PSL_FE1 so that the FP execption mode is changes to ignore.
This will prevent spurious FP exceptions being made when the running lwp
doesn't own the FPU.
2004-04-04 16:47:02 +00:00
drochner
c83eb997b8 nothing cares about __HAVE_SIGINFO anymore, so nuke it 2004-03-26 21:39:57 +00:00
matt
040b0bc071 Move data structures to softintr.c. Remove an unneeded if. Fix a typo. 2004-03-25 18:46:27 +00:00
matt
7f65c1cc37 Generic soft interrupt support for PowerPC ports. 2004-03-24 23:39:39 +00:00
matt
77effcd27e Don't waste space on likely unused sysmon structure.
Instead malloc them as needed.
2004-02-17 22:03:52 +00:00
wiz
d20841bb64 Uppercase CPU, plural is CPUs. 2004-02-13 11:36:08 +00:00
jdolecek
089abdad44 Rearrange process exit path to avoid need to free resources from different
process context ('reaper').

From within the exiting process context:
* deactivate pmap and free vmspace while we can still block
* introduce MD cpu_lwp_free() - this cleans all MD-specific context (such
  as FPU state), and is the last potentially blocking operation;
  all of cpu_wait(), and most of cpu_exit(), is now folded into cpu_lwp_free()
* process is now immediatelly marked as zombie and made available for pickup
  by parent; the remaining last lwp continues the exit as fully detached
* MI (rather than MD) code bumps uvmexp.swtch, cpu_exit() is now same
  for both 'process' and 'lwp' exit

uvm_lwp_exit() is modified to never block; the u-area memory is now
always just linked to the list of available u-areas. Introduce (blocking)
uvm_uarea_drain(), which is called to release the excessive u-area memory;
this is called by parent within wait4(), or by pagedaemon on memory shortage.
uvm_uarea_free() is now private function within uvm_glue.c.

MD process/lwp exit code now always calls lwp_exit2() immediatelly after
switching away from the exiting lwp.

g/c now unneeded routines and variables, including the reaper kernel thread
2004-01-04 11:33:29 +00:00
manu
057381d1b4 Move machine dependent definitions to machine dependent headers. 2003-12-03 18:25:44 +00:00
simonb
2350e98506 Fix some white space nits. 2003-11-26 03:56:38 +00:00
simonb
19a9d14f26 Remove the prototype for the non-existent intr_md_register() function. 2003-11-26 03:55:38 +00:00
matt
99f7a6b7db More PPC64 changes. (latent for now). 2003-11-21 22:57:14 +00:00
matt
d765841d3e Restore ci_curpm since it re-enables 603 to working state. 2003-11-21 18:07:29 +00:00
matt
13e522ee98 Add PowerPC64 definitions 2003-11-21 17:40:48 +00:00
manu
a2bed85761 Implement mach_thread_get_state.
While we are here, try to tag machine dependent functions in header files.
also transformed darwin_ppc_*_state into mach_ppc_*_state, as this is
what they really are (COMPAT_DARWIN is on the top of COMPAT_MACH, not the
other way around)
2003-11-11 17:31:59 +00:00
cl
ef56cc40ab Reduce code duplication by adding mi_userret() in sys/userret.h
containing signal posting, kernel-exit handling and sa_upcall processing.

XXX the pc532, sparc, sparc64 and vax ports should have their
XXX userret() code rearranged to use this.
2003-10-31 16:44:34 +00:00
simonb
499ef1c1bb Remove (the now non-compiling) support for 128bit FP emulation, which
isn't needed for PowerPC anyway.
2003-10-27 04:32:02 +00:00
kleink
a3fabb9e7f Use <sys/ieee754.h> where applicable. 2003-10-26 20:55:30 +00:00
matt
421dd6cc28 Reorganize the way powerpc port install machine specific headers.
Use <powerpc/oea/bat.h> exclusively and remove <machine/bat.h> and
<powerpc/bat.h>.  Remove unneeded <machine/cpufunc.h>.  To insure
1:1 correspondence of <powerpc/FOO.h> to <machine/FOO.h> include
"../../powerpc/include/Makefile" in "arch/FOO/include/Makefile".
Incororpate <byte_swap.h> into <bswap.h> and then byte_swap.h
2003-10-20 00:12:09 +00:00
matt
ba34947f80 Add powerpc-specific isa and isadma machdep code. (Merge common code from
prep and sandpoint and ...)
2003-10-19 03:19:32 +00:00
matt
4b22ee736b Add support for MPC74[45]7 2003-10-09 20:49:06 +00:00
thorpej
901da40cf9 Add some accessor macros for the ucontext:
* _UC_MACHINE_PC() - access the program counter
* _UC_MACHINE_INTRV() - access the integer return value register
* _UC_MACHINE_SET_PC() - set the program counter (this requires
  special handling on some platforms).
2003-10-08 22:43:01 +00:00
matt
60ff688f72 Define SIGTRAMP_VALID properly. 2003-09-27 00:58:32 +00:00
nathanw
4d59420344 Move __cpu_simple_lock_t and __SIMPLELOCK_{UN,}LOCKED to machine/types.h
so that they can be used in a namespace-friendly way.
2003-09-26 22:45:41 +00:00
matt
6986092cfe Add a machine-dependent SIGTRAMP_VALID macro which is used to test whether
a trampoline version is valid or not.
2003-09-26 22:14:19 +00:00
matt
2deb8b2e7b Deal with the constification of ksiginfo_t and sigset_t in signalling. 2003-09-25 22:22:36 +00:00
matt
85a5f3065d Add siginfo support for PowerPC. 2003-09-25 18:42:18 +00:00
matt
9c8a5009b3 Define va_list as __builtin_va_list for GCC 3.x. Change stdarg macros
appropriately.  (this is committed from a system run a kernel and userland
built with these changes).
2003-09-24 02:39:56 +00:00
shige
fc29eb23bf Add some PCI definitions listed in evbppc/include/walnut.h. 2003-09-23 15:19:05 +00:00
shige
2977d5a89a Add IBM40x specific machdep functions. 2003-09-23 15:14:02 +00:00
shige
87f629a7b8 Add IBM405GPr PVR. 2003-09-23 15:10:05 +00:00
manu
d13828a7dd forgotten commit for KERN_PROCARGS sysctl in COMPAT_DARWIN 2003-09-07 07:50:31 +00:00
matt
cec9cb32df Move CLKF_BASEPRI to machine specific <intr.h> file since it depends on
the encoding of the spl for the port.
2003-09-03 21:33:31 +00:00
simonb
05c33c1c05 Need to set BUS_DMA_COHERENT to BUS_DMA_NOCACHE on IBM ppc4xx CPUs.
The "emac" interface now works properly again on my Walnut.  Much
thanks to Steve Woodford for tracking this down.
2003-09-03 13:30:05 +00:00
matt
31cc6ab700 Move SFRAMELEN to frame.h and use it in vm_machdep.c. In setfunc, setup
callframe linkages correctly.  Restore use of ldptr to locore_subr.S
[pthreads and gdb no longer crash/hang the system]
2003-08-27 20:20:07 +00:00
chs
939df36e55 add support for non-executable mappings (where the hardware allows this)
and make the stack and heap non-executable by default.  the changes
fall into two basic catagories:

 - pmap and trap-handler changes.  these are all MD:
   = alpha: we already track per-page execute permission with the (software)
	PG_EXEC bit, so just have the trap handler pay attention to it.
   = i386: use a new GDT segment for %cs for processes that have no
	executable mappings above a certain threshold (currently the
	bottom of the stack).  track per-page execute permission with
	the last unused PTE bit.
   = powerpc/ibm4xx: just use the hardware exec bit.
   = powerpc/oea: we already track per-page exec bits, but the hardware only
	implements non-exec mappings at the segment level.  so track the
	number of executable mappings in each segment and turn on the no-exec
	segment bit iff the count is 0.  adjust the trap handler to deal.
   = sparc (sun4m): fix our use of the hardware protection bits.
	fix the trap handler to recognize text faults.
   = sparc64: split the existing unified TSB into data and instruction TSBs,
	and only load TTEs into the appropriate TSB(s) for the permissions.
	fix the trap handler to check for execute permission.
   = not yet implemented: amd64, hppa, sh5

 - changes in all the emulations that put a signal trampoline on the stack.
   instead, we now put the trampoline into a uvm_aobj and map that into
   the process separately.

originally from openbsd, adapted for netbsd by me.
2003-08-24 17:52:28 +00:00
matt
121c8942a6 Not all PPC ports (e.g. macppc) equate IPL_NONE with 0. 2003-08-18 22:10:33 +00:00
chs
4ba6255f14 add some 745x-specific MSSCR0 bits. 2003-08-17 18:08:17 +00:00
chs
f19809f0fa remove an unused proto. 2003-08-17 18:07:11 +00:00
matt
47483092bd Cleanup/rework cpu_switch*, switch_exit, Idle routine. Remove pcb_psl
since it was write-only.  When setting up a process, make sure the fake
callframes are properly linked together.

Only lower SPL when in Idle loop.  Raise spl to previous level (which would
be IPL_SCHED) when exiting Idle loop.  Never lower SPL anyplace else.
2003-08-12 18:34:47 +00:00
matt
c0d6cb285d Nuke ci_curpm and curpm. Nuke pcb_pmreal. Those were use for spill stacks
and those no longer exist.  for few uses that need CURPM, use CURPCB/PCB_PM
2003-08-12 05:06:53 +00:00
matt
3d5b7190ad Nuke ci_spillstk/CI_SPILLSTK. No longer needed. 2003-08-08 07:14:26 +00:00
agc
aad01611e7 Move UCB-licensed code from 4-clause to 3-clause licence.
Patches provided by Joel Baker in PR 22364, verified by myself.
2003-08-07 16:26:28 +00:00
simonb
20a37f9627 Note that the used interrupt bits are 405GP specific.
Fix a tyop.
2003-08-05 02:10:31 +00:00
matt
0e50e47bb9 Make that OEA based kernels can properly deal with kernel ISI faults. Now
that LKMs are supported, it is possible for a LKM page to be "outspilled"
resulting in a possible ISI fault.  Try to spill the page back in.
2003-08-04 22:26:59 +00:00
matt
dd1c661661 Nuke stmreg/ldmreg. PPC64 doesn't have a lmd/stmd so make sure lmw/stmw
don't invoke valid instructions on PPC64.
2003-08-02 19:40:39 +00:00
matt
c9d56ac39d Add symbolic offsets for what's in cpu save locations.
Add a PPC64 variant of mftb
2003-08-02 19:35:26 +00:00
matt
f9c46681fd Change switchframe to use register_t (anything that uses stmX/lmX needs
to be defined as register_t).
2003-07-31 15:29:29 +00:00
matt
f5444cea2f Define SZREG {4,8} appropriately. Add pseudo-instructions (via #define)
to load/store int, long, pointer, register, multiple registers.  This is so
assembly files can be support IPL32 and LP64 PowerPC implementations.
2003-07-31 06:23:55 +00:00