Commit Graph

849 Commits

Author SHA1 Message Date
nisimura 87cd634474 Put addtional checks to see the curproc is an FPA owner process. 2000-05-29 09:43:33 +00:00
nisimura 8e19d02f25 Cleanup take two
- Nuke external function reference of savefpregs() which is already defined
  in mips/cpu.h.
- Adjust the comment tells "let user processes change CP0 status register
  freely might be dangerous."
2000-05-29 09:37:00 +00:00
nisimura 3f8e9c25b6 Make claried MDP_FPUSED usage.
- MDP_FPUSED flag indicates the process has executed at least one
  FP insn during its life time.
- pcb_fpregs storage is guaranteed zero initialzed.  If the process is FPA
  owner, savefpregs() must be called to synchronize it with FPA contents.
- No necessity to save FPA contents into pcb_fpregs prior to the whole
  storage is overwritten by process_write_fpregs().
2000-05-29 09:16:36 +00:00
thorpej e03e9e8086 Rather than starting init and creating kthreads by forking and then
doing a cpu_set_kpc(), just pass the entry point and argument all
the way down the fork path starting with fork1().  In order to
avoid special-casing the normal fork in every cpu_fork(), MI code
passes down child_return() and the child process pointer explicitly.

This fixes a race condition on multiprocessor systems; a CPU could
grab the newly created processes (which has been placed on a run queue)
before cpu_set_kpc() would be performed.
2000-05-28 05:48:59 +00:00
enami 2e535006c1 No longer need to include sys/types.h. 2000-05-27 02:18:12 +00:00
soren 630f6535cd Match a comment with the MIPS3 version. 2000-05-27 02:13:46 +00:00
soren dc83d17889 Include <sys/param.h> to make the new cpu.h happy. 2000-05-27 02:13:12 +00:00
sommerfeld 40339b39f9 Reduce use of curproc in several places:
- Change ktrace interface to pass in the current process, rather than
p->p_tracep, since the various ktr* function need curproc anyway.

 - Add curproc as a parameter to mi_switch() since all callers had it
handy anyway.

 - Add a second proc argument for inferior() since callers all had
curproc handy.

Also, miscellaneous cleanups in ktrace:

 - ktrace now always uses file-based, rather than vnode-based I/O
(simplifies, increases type safety); eliminate KTRFLAG_FD & KTRFAC_FD.
Do non-blocking I/O, and yield a finite number of times when receiving
EWOULDBLOCK before giving up.

 - move code duplicated between sys_fktrace and sys_ktrace into ktrace_common.

 - simplify interface to ktrwrite()
2000-05-27 00:40:29 +00:00
thorpej a7d0570e67 First sweep at scheduler state cleanup. Collect MI scheduler
state into global and per-CPU scheduler state:

	- Global state: sched_qs (run queues), sched_whichqs (bitmap
	  of non-empty run queues), sched_slpque (sleep queues).
	  NOTE: These may collectively move into a struct schedstate
	  at some point in the future.

	- Per-CPU state, struct schedstate_percpu: spc_runtime
	  (time process on this CPU started running), spc_flags
	  (replaces struct proc's p_schedflags), and
	  spc_curpriority (usrpri of processes on this CPU).

	- Every platform must now supply a struct cpu_info and
	  a curcpu() macro.  Simplify existing cpu_info declarations
	  where appropriate.

	- All references to per-CPU scheduler state now made through
	  curcpu().  NOTE: this will likely be adjusted in the future
	  after further changes to struct proc are made.

Tested on i386 and Alpha.  Changes are mostly mechanical, but apologies
in advance if it doesn't compile on a particular platform.
2000-05-26 21:19:19 +00:00
mhitch 5228efa47e Fix typo (stray " where it shouldn't be). 2000-05-26 20:59:00 +00:00
jhawk 8e44b27348 Rename the machine-specific stack trace printing functions
from db_stack_trace_cmd() to db_stack_trace_print(),
and add an additional argument, a function pointer for an
output routine (i.e. printf() or db_printf()).

Add db_stack_trace_cmd() in db_command.[ch], calling
db_stack_trace_print() with db_printf() as the printer.

Move count==-1 special handling from db_stack_trace_print() [nee
db_stack_trace_cmd()] to db_stack_trace_cmd() [nascent here].

Again, I'm unable to test compilation on all affected platforms,
so advance apologies for potential brokenness.
2000-05-26 03:34:24 +00:00
thorpej 8964c35eca Introduce a new process state distinct from SRUN called SONPROC
which indicates that the process is actually running on a
processor.  Test against SONPROC as appropriate rather than
combinations of SRUN and curproc.  Update all context switch code
to properly set SONPROC when the process becomes the current
process on the CPU.
2000-05-26 00:36:42 +00:00
simonb 52e7cddaa7 Fix kernel profiling so that it actually works:
- Add 16 bytes to the stack on entry to _mcount so we don't
   overflow it.
 - Use inline interrupt {dis,en}abling instead of calling
   profiled function in locore.
2000-05-25 03:07:10 +00:00
soren a20a3b38fd Appease gcc. 2000-05-24 18:42:03 +00:00
thorpej 1140468205 Use preempt(), not an open-coded equivalent (which won't be
equivalent for long).
2000-05-24 16:48:33 +00:00
soren a255740671 MachForceCacheUpdate and cacheflush_bug have never been used in NetBSD,
so remove references them, and do a little other cleanup.
2000-05-23 04:21:39 +00:00
uch fb077d8092 change TX3922 D-cache mode to write-through. 2000-05-21 11:53:00 +00:00
soren f598aece87 MIPS 'mach halt' does nothing MD, so nuke it. 2000-05-21 05:41:25 +00:00
soren 6aba4259b6 R10K has 64 TLBs. 2000-05-21 04:25:57 +00:00
soren abbe53961a Add R12K PRID. 2000-05-21 04:03:34 +00:00
soren 81fa4aa07f Populate the cputype defopt (not enabled yet). 2000-05-21 03:31:35 +00:00
soren 2779a53005 Include opt_cputype.h. 2000-05-21 03:23:15 +00:00
soren 7ea4a2b744 Fix RCS ID line. 2000-05-21 02:51:58 +00:00
soren b70819c71a Also share BE ldscripts. 2000-05-21 02:50:10 +00:00
soren 135a70e5a6 Make cache printing a little more consistent. 2000-05-17 23:35:44 +00:00
soren 740759113f mips5200_FlushCache(): flush L2 cache too. 2000-05-17 12:44:48 +00:00
nisimura 66ecdc15d3 Remove unused PSL_USERCLR defines for processor status register. 2000-05-15 08:36:32 +00:00
nisimura 8a71a7a50f Backout the previous change which was done mistakenly. 2000-05-15 06:45:44 +00:00
nisimura c7c815f46b Remove #include <machine/psl.h> which is not used. 2000-05-15 06:39:14 +00:00
castor 42ccab0d49 Add fp emulation for sqrt_s and sqrt_d instructions
from Jeff Smith <jeffs@geocast.com>.  These are needed to support
-mips2 compilation.  With this change, on a QED 5231 we now pass the
paranoia tests, and are successfully using userlands built with -mips2.
2000-05-14 06:19:32 +00:00
nisimura df234d8698 Take a straight way for pagemove() PTE manipulation, abandoning to
use MIPS_TBRPL().  When PTEs are modified, both src and dst TLBs
are invalidated.  MIPS3 single TLB entry has paired double PTE
and pagemove() likely walks through multiple pages.  The positive
effect of of MachTLBUpdate() or TBRPL() is unclear.
2000-05-10 08:55:22 +00:00
nisimura de13b44edd Have mips_locoresw[] of 3 entry pointer array for different
implementation of locore routines between MIPS1 and MIPS3.  It's
independent from mips_locore_jumpvec_t which is for cache/TLB
manipulating routines peculiar to processor designs.  mips_locore_jumpvec_t
will be replaced with "processor closures" encapsulating implementation
parameters (cpuinfo) and pointers to conventaion routines (cpuops),
eventually.
2000-05-10 01:34:13 +00:00
shin a7dd7a7c0c bugfix: make sure there is no valid data in data cache, when last
mapping to the physical page is removed (R3000/MIPS1).

delete cache operations in pmap_zero_page_uncached().
2000-05-09 13:40:13 +00:00
nisimura 34a943161d Introduce mips3_TBRPL(); not used in this moment, to be useful to
discard MachTLBUpdate() calls, however, the necessity of TLB entry
modification in such a way is under question because implementation
glitches on ASID management was straightened, those calls can be
sanely removed after all.
2000-05-09 09:50:17 +00:00
nisimura 0cb6da487c Remove unused mapin(pte, v, pfnum, prot) macro. 2000-05-06 05:19:32 +00:00
thorpej 855b79db92 Let each platform typedef the new __cpu_simple_lock_t, which should
be the most efficient type used for the atomic operations in the
simplelock structure, and should also be __volatile.
2000-05-02 04:41:04 +00:00
soren e038e8aac1 No need for flushing the cache after zeroing a page uncached. 2000-04-30 23:30:47 +00:00
simonb 21666d1ea5 Only call uvm_pageidlezero() if uvm.page_idle_zero is set. 2000-04-30 23:01:24 +00:00
simonb 0ba4762798 Define offset for uvm.page_idle_zero. 2000-04-30 22:56:12 +00:00
soren f820567ce2 Allow non-pmax to use COMPAT_ULTRIX. 2000-04-29 21:47:13 +00:00
soren 082109d0e4 Move free page zeroing to before the whichqs spinner. Pointed out by simonb. 2000-04-29 14:44:42 +00:00
thorpej f51470a514 Require that each each MACHINE/MACHINE_ARCH supply a lock.h. This file
contains the values __SIMPLELOCK_LOCKED and __SIMPLELOCK_UNLOCKED, which
replace the old SIMPLELOCK_LOCKED and SIMPLELOCK_UNLOCKED.  These files
are also required to supply inline functions __cpu_simple_lock(),
__cpu_simple_lock_try(), and __cpu_simple_unlock() if locking is to be
supported on that platform (i.e. if MULTIPROCESSOR is defined in the
_KERNEL case).  Change these functions to take an int * (&alp->lock_data)
rather than the struct simplelock * itself.

These changes make it possible for userland to use the locking primitives
by including <machine/lock.h>.
2000-04-29 03:31:45 +00:00
soren 2cfb26c801 Zero free pages in the idle loop. 2000-04-28 19:25:55 +00:00
shin a332af2846 delete unused function mips3_TLBReadVPS().
reorder insns to avoid mtc0/mfc0 hazard (for VR4100/R4700/RM52xx).
save/restore PageMask in mips3_TLBRead().
2000-04-21 14:14:55 +00:00
shin e2711a6552 make it compile with -DDEBUG. 2000-04-21 14:10:39 +00:00
nisimura 79733cb614 Effort to have consistent comments, fixing one error. 2000-04-21 02:45:01 +00:00
nisimura 3d5a5b03f5 - Address PR#9907. u_pte[1] wired down is left not global sometimes.
The brokenness is revealed sporadorically by memory usage on runtime.
- Avoid Vr4100 incompatibilty by making sure to retain default pgMask
  value for TLB invalidation routines.
2000-04-21 02:39:55 +00:00
nisimura a01973aecb Change the way how pmap_protect() modifies the protection of KSEG2
space using MIPS_TBRPL() call.  It avoils to 'vistimize' a possibly
useful TLB entry. XXX MachTLBUpdate() will be retired, soon.
2000-04-16 10:16:19 +00:00
nisimura 8feff14832 Fix a typo in the previous change. 2000-04-16 10:08:32 +00:00
nisimura 4edcc4fca2 Change the way to implement zero copy data move in pagemove() using
MIPS_TBRPL().  It saves about 20 instructions to run for each
iteration, and avoids TLB polution.  Currently works for MIPS1 only
configuration.
2000-04-16 09:09:42 +00:00
nisimura 7717409808 Introduce MIPS_TBRPL() which replaces a TLB entry of given vaddr
with new entryHi and entryLo pair iff found in TLB.  Works only
for KSEG2 this moment.  mips3 version will follow.
2000-04-16 09:00:26 +00:00
soda c56a43535d remove following symbols which became unnecessary in recent cpu_intr() change:
mips_hardware_intr
	MIPS3_INTERNAL_TIMER_INTERRUPT
	mips3_intr_cycle_count
	mips3_timer_delta
2000-04-15 22:05:51 +00:00
nisimura e54e10f9ce - Withdraw dealfpu() code which has been never useful so far.
- XXX It was a mistake to add CP1 insn encoding values into cpuregs.h.
  Those will be relocated into mips_opcode.h with some adjustment work.
2000-04-15 06:21:01 +00:00
soren 0ce39b7430 Typo; user stack only needs to start one page below 0x80000000. 2000-04-13 22:02:54 +00:00
nisimura ce0937324b - Move a loop invariant of 'if (CPUISMIPS3)' out of pagemove().
- XXX I'm not sure whether the anticipatory MachTLBUpdate(to, pte) is
  a gain or loss on runtime.  If not a loss, it should be MIPS_TBIS().
2000-04-12 01:37:58 +00:00
nisimura 85f3855a8c - Implement mips3_TBIAP().
- Remove obsoluted routines in locore_mips3.S
- addiu -> addu, andi -> and, ori -> or.
2000-04-12 01:05:34 +00:00
castor 4ebaf4d105 Taken from Jeff Smith <jeffs@geocast.com>:
Fix regress/lib/libc/ieeefp/except for MIPS.  Newer FPE handling code
	did not generate SIGFPE, but always SIGILL.  Add this back to the
	assembly code.  The QED 5231 requests the kernel emulates some of
	the conditions that generate an SIGFPE, but when the emulation code
	did a ctc1 to fsr with an exception the kernel got a FPE in kernel mode.
	Fix this by saving the fp regs earlier, then saving the new FSR in
	the context.  This allows the FSR value to be seen by the SIGFPE
	handler.

	Add fp emulation for 8 mips2 fpu instructions to handle exceptions
	(round.w.fmt, trunc.w.fmt, ceil.w.fmt, floor.w.fmt).  This lets
	perl5 run when compiled -mips2.
2000-04-11 16:28:05 +00:00
nisimura aa4f967e51 Abandon rather random distinctions in andi/addiu coding and make
them consistent with and/addu instrunction mnemonics which produce
exactly same binaries.
2000-04-11 04:53:57 +00:00
nisimura dba7b560cd Load delay slot is automagically adjusted at runtime since MIPS II
architecture.
2000-04-11 04:39:14 +00:00
chs a6d33cc1f2 add a new function vn_marktext() for exec code to let others know
that the vnode is now being used as process text.
2000-04-11 04:37:47 +00:00
nisimura e342080364 Introduce cpu_intr() whose body is now provided by target ports in
their own ways.  Ugly fixup #define in machine/intr.h have gone.
mips_hardware_intr global variable patch work has gone.
2000-04-11 02:30:14 +00:00
nisimura 4f3093c121 Remove various TLB manipulation routines which have been unused
long time, commented out and is unlikely useful; TLBWriteIndexed(),
TLBWriteRandom(), TLBFlush(), TLBFlushPID() and TLBFind().
2000-04-11 01:32:19 +00:00
nisimura 53e7a8c8d5 - Fix a bug in mips1_TBIAP() misbehaving like as mips1_TBIA().
- Adjust comments to reflect what it does.
2000-04-10 11:38:16 +00:00
simonb 3d6b29f228 Use UVM_PGA_ZERO in uvm_pagealloc() calls instead of using pmap_zero_page(). 2000-04-10 08:50:20 +00:00
nisimura ea23dc6364 Make sure ASID management is done in the same way of NetBSD/alpha. Rename
and change 'pmap_alloc_asid()' into 'pmap_asid_alloc()'
2000-04-10 05:34:27 +00:00
nisimura c84ed44f75 Make (sure) ASID management same as what NetBSD/alpha does for ASN.
ASID#0 is reserved for pmap0 shared between proc0 and kthreads,
and every TLB for KSEG2 has G (global) bit to have wildcard match
regardless of the process' ASID.   MIPS1 would flush TLBs belong
to user spaces upon ASID generation bump.  Change for MIPS3 is
to be done.
2000-04-10 04:59:46 +00:00
simonb e2b66b68da Small white space and 80col wraparound cleanups. 2000-04-10 01:53:11 +00:00
soren 09ad839ab3 This file has been superseded by the MI ELF code. 2000-04-08 22:30:26 +00:00
soren aa4c70110e Move the start of the user stack down a little to account for the
virtual address checking done by the R8000 and some QED CPUs.

From Jeff Smith.
2000-04-07 21:50:08 +00:00
simonb 9edec906b5 Removing trailing comma from enum declaration. 2000-04-03 05:58:31 +00:00
thorpej 2bc5adb20e Instead of checking vm_physmem[<physseg>].pgs to determine if
uvm_page_init() has completed, add a boolean uvm.page_init_done,
and test against that.  Use this same boolean (rather than
pmap_initialized) in pmap_growkernel() to determine if we are
being called via uvm_page_init() to grow the kernel address space.

This fixes a problem on some i386 configurations where pmap_init()
itself was needing to have the kernel page table grown, and since
pmap_initialized was not yet set to TRUE, pmap_growkernel() was
choosing the wrong code path.

Fix tested by Havard Eidnes.
2000-04-02 20:39:14 +00:00
minoura 78b105698a Move dl* function definitions to libc on ELF.
Based on the patch supplied by Takuya Shiozaki <tshiozak@astec.co.jp>.
See http://mail-index.netbsd.org/tech-userlevel/2000/02/23/0000.html.
2000-04-02 15:35:47 +00:00
simonb 6e0357239a Nuke register, diddle a bit of indentation in some function declarations. 2000-03-30 14:36:30 +00:00
nisimura 1b0c1f4d0d Abandon the initial microscale optimization of pmap_alloc_asid(),
leaving the second change intact.  It'd be rather less costly to
extend the case analysis.
2000-03-28 05:58:33 +00:00
simonb 6060929e8e Move fpcurproc declaration to <mips/cpu.h>. 2000-03-28 03:11:26 +00:00
simonb ef89d70178 Don't `extern' function declarations. While we're there, remove trailing
blank lines and white space.
2000-03-28 02:58:44 +00:00
simonb ea6aa0dc3c Use the recent alpha solution to getting the printf() format right in
mips_init_msgbuf().
2000-03-28 02:53:18 +00:00
simonb 338105f94b Make declaration of curpcb variable extern. 2000-03-28 01:06:04 +00:00
simonb a833cd73e8 Remove duplicate declaration of pmap_is_page_ro() (in <mips/pte.h> and
pmap_zero_page() (in <vm/pmap.h>).
2000-03-28 01:04:22 +00:00
nisimura 464669d1ef The previous microscale optimazation in pmap_asid_alloc() was
half-baked and resulted in one superfluous ASID bump if new pmaps
are created when pmap_asid_generation > 0.   Need to initialize pmap
fields correctly.

Yet, this possibly might not be the perfect solution.  If one
process bumped pmap_asid_generation _after_ a new pmap was created
and initialized with then-current pmap_asid_generation value.  In
that case, the new pmap would have another (superfluous) ASID bump
when 2nd (not 1st) CPU tick is assigned.  I'm not sure if this case
would happen.

Have pmap_max_asid variable to hold the maximum number of ASID
(TLBpid) supported by processor anticipating the possible runtime
cost of ((CPUISMIPS3)? MIPS3_TLB_NUM_ASIDS : MIPS1_TLB_NUM_PIDS).
2000-03-28 01:00:00 +00:00
simonb 8ae7eeef11 Remove redundant declarations of mips3_cycle_count(), stacktrace(),
logstacktrace(), mips_idle() and cpu_switch() - these are already
declared in various header files.
2000-03-28 00:55:33 +00:00
simonb d0e1814cba Remove duplication declarations of Sysmap and Sysmapsize - these are
in <mips/pte.h>
2000-03-28 00:52:57 +00:00
nisimura 73fa1ce87f Change 'goto cpu_switch1' to 'goto cpu_switch_queuescan' in vr_idle.S
and make the jump destination global.
2000-03-28 00:24:04 +00:00
nisimura fa6012454d It's not necessary to (re-) assign pmap->pm_asidgen whenever ASID
(TLBpid) is bumped.  It's ok just in the case when pmap_asid_generation
is bumped.
2000-03-27 08:56:21 +00:00
nisimura 06b4feb7d6 Have TBIA/TBIAP an argument refering to a global variable instead
of a compile time constant.
2000-03-27 05:30:40 +00:00
nisimura 5987070300 - Rename some of TLB ops to have handy abbrivations hired from VAX and
ALPHA; mips1_TBIA, mips1_TBIAP, mips1_TBIS.
- Make sure TBIA and TBIAP ops to have an argument for the size of TLB
  which varies across even for MIPS1 implementations.
- Nuke the unused cpu_isa field from processor personality list.

- XXX XXX XXX
  it's less-than-optimal and likely a mistake to have TLBUpdate().
  It's costy to try to invalidate a single TLB entry whenver a certain
  PTE is going to be modified by traversing the entire TLB looking
  for the modified PTE because the PTE in question is not in TLB in
  most cases.  ASID bump could do the invalidation smartly.  Solution
  is planned for now.
2000-03-27 05:23:42 +00:00
nisimura cbab853044 Rename sw1 label found in cpu_switch() to cpu_switch_queuescan,
abandoning unnecessary .globl because switch_exit() is handsomely
common between MIPS1 and MIPS3.
2000-03-27 04:52:11 +00:00
nisimura 24571569fa Nuke MIPS_16K_PAGE conditional which should be commited in. It
was used for debugg'n purposes which only make senses on particular
hardware configurations and has never been intended to extend pagesize
of NetBSD/mips.
2000-03-27 02:55:13 +00:00
kleink 230876cf26 Merge parts of chs-ubc2 into the trunk:
* Remove the casts to vaddr_t from the round_page() and trunc_page() macros to
  make them type-generic, which is necessary i.e. to operate on file offsets
  without truncating them.
* In due course, cast pointer arguments to these macros to an appropriate
  integral type (paddr_t, vaddr_t).

Originally done by Chuck Silvers, updated by myself.
2000-03-26 20:42:21 +00:00
nisimura b6b06284ce Add QED RM7000 PrID. 2000-03-25 06:33:50 +00:00
soren 573160e03b Revert previous. 2000-03-24 23:06:03 +00:00
soren c535ede30b Move sysctl definitions from arch/mips to arch/foo. 2000-03-24 21:30:58 +00:00
soren a0c624dd3d Remove FPU PRIDs that are identical to the CPU ones. 2000-03-24 20:48:20 +00:00
soren 059fe2fbb2 One instruction per line. 2000-03-24 18:16:33 +00:00
soren 2531a231d2 Missing in previous; set cache alias mask properly on processors with
two-way set associative L1 caches.
2000-03-24 18:15:41 +00:00
nisimura 3af954d380 Have ST_REG_SR mnemonic for status register consistent with others. 2000-03-24 02:02:03 +00:00
soren 1c965174b0 Make MIPS1+MIPS3 compile again. 2000-03-23 14:49:29 +00:00
soren 64bcb49a2e Updated RM5231 cache code from Jeff Smith and Ethan Solomita at Geocast.
Many thanks.
2000-03-19 19:16:13 +00:00
tron e86957458a Install "machineendian_machdep.h". 2000-03-17 22:36:31 +00:00
mycroft 9e21b6555a In the `MY THAT'S GROSS' department...
Eliminate the recursive include of machine/endian.h from sys/endian.h.
2000-03-17 00:09:18 +00:00