http://mail-index.netbsd.org/tech-kern/2003/09/25/0007.html
We now have:
acardide* at pci? dev ? function ? # Acard IDE controllers
aceride* at pci? dev ? function ? # Acer Lab IDE controllers
cmdide* at pci? dev ? function ? # CMD tech IDE controllers
cypide* at pci? dev ? function ? # Cypress IDE controllers
hptide* at pci? dev ? function ? # Triones/HighPoint IDE controllers
optiide* at pci? dev ? function ? # Opti IDE controllers
piixide* at pci? dev ? function ? # Intel IDE controllers
pdcide* at pci? dev ? function ? # Promise IDE controllers
siside* at pci? dev ? function ? # SiS IDE controllers
slide* at pci? dev ? function ? # Symphony Labs IDE controllers
viaide* at pci? dev ? function ? # VIA/AMD/Nvidia IDE controllers
pciide* at pci? dev ? function ? flags 0x0000 # GENERIC pciide driver
serverworks driver not commited yet; there are still copyright issues about
it.
http://mail-index.netbsd.org/tech-kern/2003/09/25/0006.html
This adds a device (atabus) between IDE controllers and wd or atapibus, to
have each ATA channel show up in the device tree. Later there will be atabus
devices in /dev, so that we can do IOCTL on them.
Each atabus has its own kernel thread, to handle operations that needs polling,
e.g. reset and others.
Device probing on each bus it defered to the atabus thread creation.
This allows to do the reset and basic device probes in parallel, which reduce
boot time on systems with several pciide controllers.
1) Don't wait for DRQ on an IDENTIFY command -- if it's not set when we see
BSY clear, abort the command and ignore the drive. (Do this by testing
for DRQ in the read/write cases in __wdccommand_intr().)
2) Don't wait for DRQ to deassert when we finish an IDENTIFY (or any other
non-block command that reads data) -- we don't do this for block I/O, and
empirically it doesn't clear on my CF cards at all, causing a pointless 1s
delay.
3) Add comments to some of the delay()s, and add missing ones in wdcreset()
and the WDCC_RECAL in the so-called "pre-ATA" probe.
4) Slightly simplify the reset sequence -- we were doing an extra I/O.
5) Modify the register writability test to make sure that registers are not
overlapped -- this can happen in some weird cases with a missing device 1.
6) Check the error register value after the reset -- if it's not 01h or 81h,
as appropriate (see ATA spec), punt.
Tested with a number of ATA-only, ATAPI-only, mixed ATA-ATAPI, CF, and IDE
disk configurations.
Also remove the SINGLE_DRIVE nonsense again.
most polling.
2) Clean up some goofiness in pciide -- get rid of the whole "candisable" path
(it's gratuitous) and simplify the code by calling pciide_map_compat_intr(),
*_set_modes() and wdc_print_modes() from central locations.
3) Add a register writability and register ghost test to eliminate phantom
drives more quickly.
This wasn't an error, on this chipset we have the SATA controller on function
0 of the IDE controller, not the pcib bridge.
Fix provided by Stephen Degler.
We only support legacy (i.e. PCI IDE compatible) mode, for now. Also
note that DMA is disabled for rev 0 chips unless explicitly enabled
with PCIIDE_I31244_ENABLEDMA.
Such RAID controllers are actually just IDE controllers with a BIOS that
can create RAID volumes and write the configuration info to config blocks
on the disks. The BIOS can do I/O to these volumes, and the OS must
understand the config blocks and implement RAID in software in order to be
able to use these volumes.
Only SPAN (simple concatenation) and RAID0 are supported at this time,
and writing back config blocks is also not supported at this time. Currently,
only the Promise configuration scheme is supported, although supporting
the Highpoint scheme should not be too difficult.
In any case, this is sufficient to use the Promise RAID0 volume (thus
preserving the win2k AS installation) on this new Intel server I have.
Thanks to Soren Schmidt for doing the work in FreeBSD; it made this
task much easier. The config block parsing code is adapted from his
work.
IDE controllers, which are more-or-less compatible with the
AMD controllers.
XXX Need to determine the correct timing value for the nForce2
XXX at Ultra133, so we cap it at Ultra100, for now.
pdc202xx_setup_channel, pdc20268_setup_channel:
Properly compute the address of the DMA control register for channel 1.
I think the controllers ignore these bits, I suspect it's only there so that
the BIOS can tell the OS is has configured DMA, but better be correct.
Thanks to Alexander Yurchenko for pointing this out.
on current-users, with cross-check and some improvement from linux-2.4.19
and FreeBSD-current.
Also don't set the APO_UDMA_CLK66 bit for Ultra/100 capable chipset, and
support Ultra/133 for the VT8233A.
bouyer