Make DMA mode works on Promise Ultra66/100 with 48-bit LBA drives.
Ok'ed by bouyer in tech-kern@netbsd.org.
This commit is contained in:
nakayama
parent
4661d01ee2
commit
1e411d7027
@ -1,4 +1,4 @@
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/* $NetBSD: ata_wdc.c,v 1.38 2002/09/27 15:37:09 provos Exp $ */
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/* $NetBSD: ata_wdc.c,v 1.39 2003/04/28 05:20:29 nakayama Exp $ */
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/*
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* Copyright (c) 1998, 2001 Manuel Bouyer.
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@ -68,7 +68,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: ata_wdc.c,v 1.38 2002/09/27 15:37:09 provos Exp $");
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__KERNEL_RCSID(0, "$NetBSD: ata_wdc.c,v 1.39 2003/04/28 05:20:29 nakayama Exp $");
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#ifndef WDCDEBUG
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#define WDCDEBUG
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@ -271,6 +271,8 @@ _wdc_ata_bio_start(chp, xfer)
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if (drvp->n_xfers <= NXFER)
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drvp->n_xfers++;
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dma_flags = (ata_bio->flags & ATA_READ) ? WDC_DMA_READ : 0;
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if (ata_bio->flags & ATA_LBA48)
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dma_flags |= WDC_DMA_LBA48;
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}
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if (ata_bio->flags & ATA_SINGLE)
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ata_delay = ATA_DELAY;
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@ -1,4 +1,4 @@
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/* $NetBSD: wdcvar.h,v 1.35 2003/01/27 18:21:26 thorpej Exp $ */
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/* $NetBSD: wdcvar.h,v 1.36 2003/04/28 05:20:30 nakayama Exp $ */
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/*-
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* Copyright (c) 1998 The NetBSD Foundation, Inc.
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@ -124,8 +124,9 @@ struct wdc_softc { /* Per controller state */
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void (*dma_start) __P((void *, int, int));
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int (*dma_finish) __P((void *, int, int, int));
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/* flags passed to dma_init */
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#define WDC_DMA_READ 0x01
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#define WDC_DMA_IRQW 0x02
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#define WDC_DMA_READ 0x01
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#define WDC_DMA_IRQW 0x02
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#define WDC_DMA_LBA48 0x04
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int dma_status; /* status returned from dma_finish() */
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#define WDC_DMAST_NOIRQ 0x01 /* missing IRQ */
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#define WDC_DMAST_ERR 0x02 /* DMA error */
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@ -1,4 +1,4 @@
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/* $NetBSD: pciide.c,v 1.190 2003/04/19 23:37:26 christos Exp $ */
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/* $NetBSD: pciide.c,v 1.191 2003/04/28 05:20:31 nakayama Exp $ */
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/*
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@ -76,7 +76,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: pciide.c,v 1.190 2003/04/19 23:37:26 christos Exp $");
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__KERNEL_RCSID(0, "$NetBSD: pciide.c,v 1.191 2003/04/28 05:20:31 nakayama Exp $");
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#ifndef WDCDEBUG
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#define WDCDEBUG
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@ -210,6 +210,8 @@ void pdc202xx_setup_channel __P((struct channel_softc*));
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void pdc20268_setup_channel __P((struct channel_softc*));
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int pdc202xx_pci_intr __P((void *));
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int pdc20265_pci_intr __P((void *));
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static void pdc20262_dma_start __P((void*, int, int));
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static int pdc20262_dma_finish __P((void*, int, int, int));
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void opti_chip_map __P((struct pciide_softc*, struct pci_attach_args*));
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void opti_setup_channel __P((struct channel_softc*));
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@ -4337,6 +4339,13 @@ pdc202xx_chip_map(sc, pa)
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sc->sc_wdcdev.channels = sc->wdc_chanarray;
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sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS;
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if (sc->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA66 ||
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sc->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 ||
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sc->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X) {
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sc->sc_wdcdev.dma_start = pdc20262_dma_start;
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sc->sc_wdcdev.dma_finish = pdc20262_dma_finish;
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}
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if (!PDC_IS_268(sc)) {
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/* setup failsafe defaults */
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mode = 0;
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@ -4663,6 +4672,61 @@ pdc20265_pci_intr(arg)
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return rv;
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}
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static void
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pdc20262_dma_start(v, channel, drive)
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void *v;
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int channel, drive;
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{
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struct pciide_softc *sc = v;
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struct pciide_dma_maps *dma_maps =
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&sc->pciide_channels[channel].dma_maps[drive];
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int atapi;
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if (dma_maps->dma_flags & WDC_DMA_LBA48) {
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atapi = (dma_maps->dma_flags & WDC_DMA_READ) ?
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PDC262_ATAPI_LBA48_READ : PDC262_ATAPI_LBA48_WRITE;
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atapi |= dma_maps->dmamap_xfer->dm_mapsize >> 1;
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bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh,
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PDC262_ATAPI(channel), atapi);
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}
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pciide_dma_start(v, channel, drive);
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}
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int
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pdc20262_dma_finish(v, channel, drive, force)
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void *v;
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int channel, drive;
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int force;
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{
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struct pciide_softc *sc = v;
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struct pciide_dma_maps *dma_maps =
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&sc->pciide_channels[channel].dma_maps[drive];
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struct channel_softc *chp;
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int atapi, error;
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error = pciide_dma_finish(v, channel, drive, force);
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if (dma_maps->dma_flags & WDC_DMA_LBA48) {
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chp = sc->wdc_chanarray[channel];
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atapi = 0;
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if (chp->ch_drive[0].drive_flags & DRIVE_ATAPI ||
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chp->ch_drive[1].drive_flags & DRIVE_ATAPI) {
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if ((!(chp->ch_drive[0].drive_flags & DRIVE_UDMA) ||
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(chp->ch_drive[1].drive_flags & DRIVE_UDMA) ||
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!(chp->ch_drive[1].drive_flags & DRIVE_DMA)) &&
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(!(chp->ch_drive[1].drive_flags & DRIVE_UDMA) ||
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(chp->ch_drive[0].drive_flags & DRIVE_UDMA) ||
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!(chp->ch_drive[0].drive_flags & DRIVE_DMA)))
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atapi = PDC262_ATAPI_UDMA;
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}
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bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh,
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PDC262_ATAPI(channel), atapi);
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}
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return error;
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}
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void
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opti_chip_map(sc, pa)
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struct pciide_softc *sc;
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@ -1,4 +1,4 @@
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/* $NetBSD: pciide_pdc202xx_reg.h,v 1.8 2002/07/26 14:11:35 wiz Exp $ */
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/* $NetBSD: pciide_pdc202xx_reg.h,v 1.9 2003/04/28 05:20:33 nakayama Exp $ */
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/*
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* Copyright (c) 1999 Manuel Bouyer.
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@ -99,6 +99,8 @@
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#define PDC262_ATAPI_DMA_READ 0x00001000
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#define PDC262_ATAPI_DMA_WRITE 0x00002000
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#define PDC262_ATAPI_UDMA 0x00004000
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#define PDC262_ATAPI_LBA48_READ 0x05000000
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#define PDC262_ATAPI_LBA48_WRITE 0x06000000
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/*
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* The timings provided here cmoes from the PDC20262 docs. I hope they are
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