- centralize pcmcia function allocation and free'ing.
- free the cfe too, not just the pf in the multifunction card case.
- don't free pointers while walking the list, because free() will
fill the memory with deadbeef, thus killing list walking.
of the range are aligned to a cacheline boundary, when do a dcache-inv
operation, rather than a dcache-wbinv operation.
XXX It could be a little smarter (align using wbinv, inv, then finish
up using wbinv), but even this simple change is good for a nearly 40%
improvement in my test case on XScale.
condition on a branch (bpl where bhi should have been used). The error
caused one more line than intended to be flushed, which is particularly
bad if you're doing a dcache-invalidate operation.
map contains "coherent" (non-cached in ARM-land) mappings.
* Set ARM32_DMAMAP_COHERENT in the map at the start of a load operation,
and clear it in _bus_dmamap_load_buffer() if we encounter any cacheable
mappings.
* In _bus_dmamap_sync(), if the map is marked COHERENT, skip any cache
flushing.
longer a forced correspondence between bit numbers in an interrupt
register and bit numbers in an spl mask. This will avoid conflicts
between various interrupt registers in the same system.
Instead, bits in the spl mask are allocated on a first come, first
served basis by devices which can interrupt. The new hp700_intr_ipending_new
takes care of reading all interrupt request registers that need
servicing, and mapping the bits set in those registers to new bits
set in ipending.
This whole mechanism is in and works. A later commit will see the
I/O subsystems fixing which bits in their interrupt registers are
connected to which devices, largely removing irq information from
kernel configuration files. There will also be a cosmetic fix to
show which spl bit corresponds to a device.
* Replace __byte_swap_32_variable() with a C version from Richard
Earnshaw that generates nearly identical assembly (and it would be
exactly identical with the addition of another peephole to GCC ARM
back-end).
pmap_copy_page, and pmap_clear_modify (pmap_clear_bit). Remove #ifdef
MULTIPROCESSOR since the cache instructions operate on all caches on
all processors.
optimization made last year. should solve PR 17867 and 10195.
IP_HDRINCL behavior of raw ip socket is kept unchanged. we may want to
provide IP_HDRINCL variant that does not swap endian.
* Byte-swap 16-bit and 32-bit constants at compile-time.
* Inline 16-bit and 32-bit variable byte-swaps. These take 3 and 4
insns, respectively, and inlining saves the minimum 6 cycle penalty
to call/return from the byte swap function.
