Check only the IR bit of the CIAA Interrupt Control Register when testing
for a level 6 interrupt. An interrupt only occurs if IR is set, and IR is
only set if the individual mask bits are set. The individual interrupt
status bits can be set without causing an interrupt if the corresponding
enable bits are not set.
from arch/mips/mips/locore.S to arch/pmax/pmax/locore_machdep.S.
* Move ARC-specific locore code (vmstat -i counters) to
arch/pica/pica/locore_machdep.S.
* When the mips3 locore support is known to work, both ports can now use
arch/mips/mips/locore.S.
wrappers for:
gets.c getenv.c strcat.c strcpy.c
so they compile again (if _KERNEL is defined).
For bootblock space reasons it would be prereable to call the PROM entrypoints
directly, via the macro wappers in de_prom.h, rather than C function wrappers.
* Create arch/mips/Makefile.inc with source list of generic MIPS-cpu
files for tags
* Use mips/Makefile.inc and updated tag list in pmax/Makefile
* Try building bootblocks in arch/pmax/stand.
clock_attach() time (for now).
This removes our dependance on the DraCo ROM access timing and frees
the second CIA on Amigas.
b) support for DraCo rev. >= 4 native timer chips.
* When we are transferring in DATA (in asc_dma_in) and the target
is an async device, there is sometimes an extra byte in the FIFO.
If so, we need to drain that byte out of the fifo, but if and only
if the target is async. See also the comments in asc_dma_in()
in the related Mach mk84 asc driver (scsi_53C94_hdw.c), which
has an identical fix but applied in more restrictive conditions
than we need, with async *disk* targets, as well as async tapes.
* Add a watchdog and timeout active SCSI requests, to eliminate any
potential for deadlock due to applying the fix above on newer
silicon versions of the 53c94 which may not have the above problem.
Should use the MI scsi per-target timeout instead, when available.
for a level 6 interrupt. An interrupt only occurs if IR is set, and IR is
only set if the individual mask bits are set. The individual interrupt
status bits can be set without causing an interrupt if the corresponding
enable bits are not set.
NOTE: THESE FILES ARE NOW IDENTICAL TO THEIR ALPHA COUNTERPARTS.
The C preprocessor does the Right Thing when these files are built
on a SPARC. This makes it significantly easier to diff the two
versions (until a real MI 53c9x driver is done, hint hint).
* Handle message retransmissions and partially sent messages correctly.
* Make sure we clear ATN after the last message is sent.
* Do the right thing if the target initiates negotiation for async mode
after having negotiated sync mode.
* Fix some cases where we set ATN with no message queued, or schedule a
message without setting ATN.
* Issue a REQUEST SENSE after an unexpected disconnect, per SCSI spec.
* Fix abort handling in a number of cases.
* Recognize selection timeouts better (to speed up probing).
ELF-outputting version of the assembler. (It was dying when it saw
some CPP line number markers.) This is temporary. (Workaround suggested
by Matt Thomas.)
would generate two interrupts, one real and one spurious. The solution
is to force a drain of the SBus->MBus write buffers after writing to the
lance to clear the interrupt. Thanks to Chris Torek for pointing out a much
easier way to do this than I had planned...
