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Check only the IR bit of the CIAB Interrupt Control Register when testing

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for a level 6 interrupt.  An interrupt only occurs if IR is set, and IR is
only set if the individual mask bits are set.  The individual interrupt
status bits can be set without causing an interrupt if the corresponding
enable bits are not set.
This commit is contained in:
mhitch 1996-09-28 15:45:41 +00:00
parent 8e6bc9ed5f
commit 3a51f86499
1 changed files with 2 additions and 3 deletions
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5
sys/arch/amiga/amiga/locore.s
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@ -1,4 +1,4 @@
/* $NetBSD: locore.s,v 1.59 1996/06/13 19:12:25 is Exp $ */
/* $NetBSD: locore.s,v 1.60 1996/09/28 15:45:41 mhitch Exp $ */
/*
* Copyright (c) 1988 University of Utah.
@ -654,8 +654,7 @@ _fake_lev6intr:
CIABADDR(a0)
movb a0@(CIAICR),d0 | read irc register (clears ints!)
tstb d0 | check if CIAB was source
jeq Lchkexter | no, go through isr chain
jge Lchkexter | CIAB IR not set, go through isr chain
INTREQWADDR(a0)
#ifndef LEV6_DEFER
movew #INTF_EXTER,a0@ | clear EXTER interrupt in intreq