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Fix long-standing bug with Lance ethernet and Sun4m's, where each packet 

would generate two interrupts, one real and one spurious. The solution
is to force a drain of the SBus->MBus write buffers after writing to the
lance to clear the interrupt. Thanks to Chris Torek for pointing out a much
easier way to do this than I had planned...
This commit is contained in:
abrown 1996-09-27 15:11:43 +00:00
parent 0f40954572
commit d7ef005a81
1 changed files with 13 additions and 10 deletions
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23
sys/arch/sparc/dev/if_le.c
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@ -1,4 +1,4 @@
/* $NetBSD: if_le.c,v 1.36 1996/07/06 00:01:34 abrown Exp $ */
/* $NetBSD: if_le.c,v 1.37 1996/09/27 15:11:43 abrown Exp $ */
/*-
* Copyright (c) 1996
@ -89,15 +89,7 @@ myleintr(arg)
if (lesc->sc_dma->sc_regs->csr & D_ERR_PEND)
return ledmaintr(lesc->sc_dma);
/*
* XXX There is a bug somewhere in the interrupt code that causes stray
* ethernet interrupts under high network load. This bug has been
* impossible to locate, so until it is found, we just ignore stray
* interrupts, as they do not in fact correspond to dropped packets.
*/
/* return */ am7990_intr(arg);
return 1;
return am7990_intr(arg);
}
#endif
@ -116,9 +108,20 @@ lewrcsr(sc, port, val)
u_int16_t port, val;
{
register struct lereg1 *ler1 = ((struct le_softc *)sc)->sc_r1;
#if defined(SUN4M)
volatile u_int16_t discard;
#endif
ler1->ler1_rap = port;
ler1->ler1_rdp = val;
#if defined(SUN4M)
/*
* We need to flush the Sbus->Mbus write buffers. This can most
* easily be accomplished by reading back the register that we
* just wrote (thanks to Chris Torek for this solution).
*/
discard = ler1->ler1_rdp;
#endif
}
hide u_int16_t