28 lines
1.1 KiB
C
28 lines
1.1 KiB
C
/* Unicorn Emulator Engine */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2015 */
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/* Modified for Unicorn Engine by Chen Huitao<chenhuitao@hfmrit.com>, 2020 */
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#ifndef UC_QEMU_TARGET_RISCV_H
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#define UC_QEMU_TARGET_RISCV_H
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// functions to read & write registers
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int riscv_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals,
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int count);
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int riscv_reg_write(struct uc_struct *uc, unsigned int *regs, void *const *vals,
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int count);
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int riscv32_context_reg_read(struct uc_context *ctx, unsigned int *regs,
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void **vals, int count);
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int riscv32_context_reg_write(struct uc_context *ctx, unsigned int *regs,
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void *const *vals, int count);
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int riscv64_context_reg_read(struct uc_context *ctx, unsigned int *regs,
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void **vals, int count);
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int riscv64_context_reg_write(struct uc_context *ctx, unsigned int *regs,
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void *const *vals, int count);
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void riscv_reg_reset(struct uc_struct *uc);
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void riscv32_uc_init(struct uc_struct *uc);
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void riscv64_uc_init(struct uc_struct *uc);
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#endif
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