unicorn/qemu/target/riscv
2021-11-21 16:44:39 +01:00
..
insn_trans import Unicorn2 2021-10-03 22:14:44 +08:00
riscv32 import Unicorn2 2021-10-03 22:14:44 +08:00
riscv64 import Unicorn2 2021-10-03 22:14:44 +08:00
cpu_bits.h import Unicorn2 2021-10-03 22:14:44 +08:00
cpu_helper.c import Unicorn2 2021-10-03 22:14:44 +08:00
cpu_user.h import Unicorn2 2021-10-03 22:14:44 +08:00
cpu-param.h import Unicorn2 2021-10-03 22:14:44 +08:00
cpu.c Format 2021-11-04 19:58:44 +01:00
cpu.h import Unicorn2 2021-10-03 22:14:44 +08:00
csr.c import Unicorn2 2021-10-03 22:14:44 +08:00
fpu_helper.c import Unicorn2 2021-10-03 22:14:44 +08:00
helper.h Leave out size parameter in callback 2021-11-09 00:21:34 +01:00
instmap.h import Unicorn2 2021-10-03 22:14:44 +08:00
op_helper.c import Unicorn2 2021-10-03 22:14:44 +08:00
pmp.c import Unicorn2 2021-10-03 22:14:44 +08:00
pmp.h import Unicorn2 2021-10-03 22:14:44 +08:00
README import Unicorn2 2021-10-03 22:14:44 +08:00
translate.c Inline uc_tracecode when there is only exactly one hook 2021-11-21 16:44:39 +01:00
unicorn.c Add RISCV CSR registers 2021-11-07 20:36:04 +01:00
unicorn.h Add clang-format and format code to qemu code style 2021-10-29 12:44:49 +02:00

code under riscv32/ is from riscv32-softmmu/target/riscv/*.inc.c
code under riscv64/ is from riscv64-softmmu/target/riscv/*.inc.c

WARNING: these code are autogen from scripts/decodetree.py, DO NOT modify them.