unicorn/qemu/target/riscv
lazymio 9427f0a553
Merge pull request #1991 from apparentlymart/b-riscv-invalidinsn-pcadj
riscv: Invalid 32-bit instruction should not decrement pc
2024-09-21 18:26:59 +08:00
..
insn_trans import Unicorn2 2021-10-03 22:14:44 +08:00
riscv32 import Unicorn2 2021-10-03 22:14:44 +08:00
riscv64 import Unicorn2 2021-10-03 22:14:44 +08:00
cpu_bits.h target/riscv: fix wfi exception behavior 2024-09-03 13:44:55 -07:00
cpu_helper.c import Unicorn2 2021-10-03 22:14:44 +08:00
cpu_user.h import Unicorn2 2021-10-03 22:14:44 +08:00
cpu-param.h import Unicorn2 2021-10-03 22:14:44 +08:00
cpu.c Remove MMU hacks 2023-03-28 14:02:17 +02:00
cpu.h import Unicorn2 2021-10-03 22:14:44 +08:00
csr.c import Unicorn2 2021-10-03 22:14:44 +08:00
fpu_helper.c import Unicorn2 2021-10-03 22:14:44 +08:00
helper.h Leave out size parameter in callback 2021-11-09 00:21:34 +01:00
instmap.h import Unicorn2 2021-10-03 22:14:44 +08:00
op_helper.c target/riscv: fix wfi exception behavior 2024-09-03 13:44:55 -07:00
pmp.c import Unicorn2 2021-10-03 22:14:44 +08:00
pmp.h import Unicorn2 2021-10-03 22:14:44 +08:00
README import Unicorn2 2021-10-03 22:14:44 +08:00
translate.c riscv: Invalid 32-bit instruction should not decrement pc 2024-08-28 14:06:17 -07:00
unicorn.c Simplify reg_read/reg_write, obtaining a perf boost. 2023-06-16 15:23:42 -07:00
unicorn.h Simplify reg_read/reg_write, obtaining a perf boost. 2023-06-16 15:23:42 -07:00

code under riscv32/ is from riscv32-softmmu/target/riscv/*.inc.c
code under riscv64/ is from riscv64-softmmu/target/riscv/*.inc.c

WARNING: these code are autogen from scripts/decodetree.py, DO NOT modify them.