b0ea433772
Access to TB, DEC registers was lead to crash spr_read_decr and others are changed to spr_read_generic spr_write_decr and others are changed to spr_write_generic
127 lines
3.4 KiB
C
127 lines
3.4 KiB
C
#include "unicorn_test.h"
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const uint64_t code_start = 0x1000;
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const uint64_t code_len = 0x4000;
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static void uc_common_setup(uc_engine **uc, uc_arch arch, uc_mode mode,
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const char *code, uint64_t size)
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{
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OK(uc_open(arch, mode, uc));
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OK(uc_mem_map(*uc, code_start, code_len, UC_PROT_ALL));
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OK(uc_mem_write(*uc, code_start, code, size));
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}
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static void test_ppc32_add(void)
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{
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uc_engine *uc;
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char code[] = "\x7f\x46\x1a\x14"; // ADD 26, 6, 3
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int reg;
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uc_common_setup(&uc, UC_ARCH_PPC, UC_MODE_32 | UC_MODE_BIG_ENDIAN, code,
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sizeof(code) - 1);
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reg = 42;
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OK(uc_reg_write(uc, UC_PPC_REG_3, ®));
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reg = 1337;
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OK(uc_reg_write(uc, UC_PPC_REG_6, ®));
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OK(uc_emu_start(uc, code_start, code_start + sizeof(code) - 1, 0, 0));
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OK(uc_reg_read(uc, UC_PPC_REG_26, ®));
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TEST_CHECK(reg == 1379);
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OK(uc_close(uc));
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}
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// https://www.ibm.com/docs/en/aix/7.2?topic=set-fadd-fa-floating-add-instruction
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static void test_ppc32_fadd(void)
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{
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uc_engine *uc;
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char code[] = "\xfc\xc4\x28\x2a"; // fadd 6, 4, 5
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uint32_t r_msr;
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uint64_t r_fpr4, r_fpr5, r_fpr6;
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uc_common_setup(&uc, UC_ARCH_PPC, UC_MODE_32 | UC_MODE_BIG_ENDIAN, code,
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sizeof(code) - 1);
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OK(uc_reg_read(uc, UC_PPC_REG_MSR, &r_msr));
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r_msr |= (1 << 13); // Big endian
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OK(uc_reg_write(uc, UC_PPC_REG_MSR, &r_msr)); // enable FP
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r_fpr4 = 0xC053400000000000ul;
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r_fpr5 = 0x400C000000000000ul;
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OK(uc_reg_write(uc, UC_PPC_REG_FPR4, &r_fpr4));
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OK(uc_reg_write(uc, UC_PPC_REG_FPR5, &r_fpr5));
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OK(uc_emu_start(uc, code_start, code_start + sizeof(code) - 1, 0, 0));
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OK(uc_reg_read(uc, UC_PPC_REG_FPR6, &r_fpr6));
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TEST_CHECK(r_fpr6 == 0xC052600000000000ul);
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OK(uc_close(uc));
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}
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static void test_ppc32_sc_cb(uc_engine *uc, uint32_t intno, void *data)
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{
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uc_emu_stop(uc);
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return;
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}
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static void test_ppc32_sc(void)
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{
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uc_engine *uc;
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char code[] = "\x44\x00\x00\x02"; // sc
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uint32_t r_pc;
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uc_hook h;
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uc_common_setup(&uc, UC_ARCH_PPC, UC_MODE_32 | UC_MODE_BIG_ENDIAN, code,
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sizeof(code) - 1);
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OK(uc_hook_add(uc, &h, UC_HOOK_INTR, test_ppc32_sc_cb, NULL, 1, 0));
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OK(uc_emu_start(uc, code_start, code_start + sizeof(code) - 1, 0, 0));
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OK(uc_reg_read(uc, UC_PPC_REG_PC, &r_pc));
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TEST_CHECK(r_pc == code_start + 4);
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OK(uc_close(uc));
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}
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static void test_ppc32_cr(void)
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{
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uc_engine *uc;
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uint32_t r_cr = 0x12345678;
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uc_common_setup(&uc, UC_ARCH_PPC, UC_MODE_32 | UC_MODE_BIG_ENDIAN, NULL, 0);
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OK(uc_reg_write(uc, UC_PPC_REG_CR, &r_cr));
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r_cr = 0;
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OK(uc_reg_read(uc, UC_PPC_REG_CR, &r_cr));
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TEST_CHECK(r_cr == 0x12345678);
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OK(uc_close(uc));
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}
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static void test_ppc32_spr_time(void)
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{
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char code[] = ("\x7c\x76\x02\xa6" // mfspr r3, DEC
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"\x7c\x6d\x42\xa6" // mfspr r3, TBUr
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);
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uc_engine *uc;
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uc_common_setup(&uc, UC_ARCH_PPC, UC_MODE_32 | UC_MODE_BIG_ENDIAN, code,
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sizeof(code) - 1);
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OK(uc_emu_start(uc, code_start, code_start + sizeof(code) - 1, 0, 0));
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OK(uc_close(uc));
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}
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TEST_LIST = {{"test_ppc32_add", test_ppc32_add},
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{"test_ppc32_fadd", test_ppc32_fadd},
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{"test_ppc32_sc", test_ppc32_sc},
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{"test_ppc32_cr", test_ppc32_cr},
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{"test_ppc32_spr_time", test_ppc32_spr_time},
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{NULL, NULL}}; |