Commit Graph

2710 Commits

Author SHA1 Message Date
Amarachi Omereife
dec01d7223 code refactor 2023-10-17 11:30:20 +01:00
Amarachi Omereife
dfdf7e7cd1 create artifacts folder 2023-10-15 13:02:15 +01:00
Amarachi Omereife
f9a1b49c2b refactor 2023-10-15 12:46:18 +01:00
Amarachi Omereife
efc9d9ad8e workflow dispatch 2023-10-15 12:38:02 +01:00
Amarachi Omereife
a5f7059a34 attach-release 2023-10-15 12:21:50 +01:00
lazymio
d4b92485b1
Remove stale bot 2023-06-17 23:51:46 +02:00
lazymio
7b8c63dfe6
Exclude enhancement and bug issues 2023-02-07 10:44:36 +01:00
mio
56f3bdedb4
Update ChangeLog 2022-11-22 21:55:02 +01:00
mio
e9c1c17f6d
Fix endianess detection 2022-11-16 15:16:49 +01:00
mio
5f5ef1546c
Update CMakeLists versions 2022-11-16 15:01:49 +01:00
mio
6954396ae5
Merge branch 'master' into dev 2022-11-16 15:01:09 +01:00
Nguyen Anh Quynh
a16f4ff911 python: update list of supported archs in setup.py 2022-11-02 00:28:40 +08:00
Nguyen Anh Quynh
241a391cec Merge branch 'dev' 2022-11-01 23:36:54 +08:00
mio
db9ddabf9e
Update bindings 2022-11-01 10:06:34 +01:00
mio
bdd9f4fa9a
Bump version to 2.0.1 2022-11-01 10:06:22 +01:00
mio
d9c241d5f4
Update FAQ 2022-11-01 10:04:59 +01:00
Nguyen Anh Quynh
3c53a64e30 Merge branch 'dev' 2022-11-01 13:56:59 +08:00
mio
e6da816803
Update changelog 2022-10-31 16:09:06 +01:00
Nguyen Anh Quynh
8ac20e2012 python: add some more comments for samples 2022-10-31 12:37:18 +08:00
Nguyen Anh Quynh
951f155f0a Update SECURITY.md 2022-10-31 12:35:37 +08:00
Nguyen Anh Quynh
896416b350
Update SECURITY.md 2022-10-29 01:32:05 +08:00
mio
fc193ffe24
Fix missing macros 2022-10-28 17:55:39 +02:00
mio
a40bf26263
Disable test_x86_unaligned_access on be hosts 2022-10-28 17:53:20 +02:00
mio
428ed8fd21
Fix test_x86_unaligned_access for big endian hosts 2022-10-28 17:47:55 +02:00
mio
563104fa91
IP register is 2 bytes 2022-10-28 17:44:17 +02:00
mio
9c5358c759
Respect QEMU ZMM_Q to work on big endian hosts 2022-10-28 17:37:02 +02:00
mio
3c18ddcc41
Fix PC write for PPC32/64 2022-10-28 16:23:50 +02:00
mio
4b961a8ef6
Apply fix for big endian hosts per #1710 2022-10-28 16:20:20 +02:00
mio
98980c904c
Pass the correct size integers 2022-10-28 15:59:14 +02:00
mio
47275c18f4
Fix a test bug 2022-10-28 15:02:59 +02:00
mio
d80cd54b0f
Revert test_ctl endian changes 2022-10-27 23:39:43 +02:00
mio
bb7b5bb64a
Use macro bswap 2022-10-27 23:32:15 +02:00
mio
e01556557e
Fix endianess in test_ctl 2022-10-27 22:52:25 +02:00
mio
fb8fb1ca7a
Add headers for endianess 2022-10-27 22:51:56 +02:00
mio
da3999b6f0
Add tests for thumb2 2022-10-21 11:37:07 +02:00
mio
6162708bb2
Hack more to support BE32 2022-10-21 11:30:22 +02:00
lazymio
c30a712058
Merge pull request #1723 from TSRBerry/update-dotnet
bindings: Refactor and update .NET bindings
2022-10-20 22:01:22 +02:00
mio
3ea7857be3
Exit early when invalid read happens
In this way, the target register won't be overwritten
2022-10-20 21:57:28 +02:00
mio
e5756b79f8
Update FAQ 2022-10-20 21:47:09 +02:00
TSR Berry
040146e059
dotnet: Target .NET 6.0 2022-10-20 21:31:46 +02:00
mio
13b8e2625f
Check PC range for mem hooks 2022-10-20 21:25:21 +02:00
mio
a5d4d30a31
Sync PC for mem ldst on aarch64 2022-10-20 21:19:18 +02:00
TSR Berry
0522f728b6
dotnet: Remove faulty property groups 2022-10-20 20:35:54 +02:00
mio
35010035d7
Fix macro typo
Thanks @roehling
2022-10-20 20:10:27 +02:00
lazymio
df3aa0fccb
Merge pull request #1722 from TSRBerry/dev
aarch64: Add FPCR and FPSR registers
2022-10-15 00:17:38 +02:00
TSR Berry
7b8b75b9f8
bindings: Adjust consts 2022-10-14 17:33:07 +02:00
TSR Berry
442dd437e1
aarch64: Move FPCR and FPSR registers to not break compatibility
Co-authored-by: merry <git@mary.rs>
2022-10-14 17:31:20 +02:00
TSR Berry
b1af49f72b
dotnet: Adapt README.md to recent changes 2022-10-14 17:16:57 +02:00
TSR Berry
ff1f0a5c1a
dotnet: Refactor .NET bindings for .NET5.0 2022-10-14 16:57:46 +02:00
TSR Berry
c787fa8e64
bindings: Update Arm64 consts 2022-10-14 15:18:16 +02:00