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958 Commits

Author SHA1 Message Date
Nguyen Anh Quynh 80b0356a86 fix a comment in uc_hook_add() for UC_HOOK_INSN 2016-02-11 09:27:30 +08:00
Nguyen Anh Quynh 0822c0af85 bump API version to 1.0 2016-02-11 08:05:15 +08:00
Nguyen Anh Quynh a7a1dcc661 uc_hook_add(): add begin & end arguments for all hook types. also update Python binding after this change 2016-02-11 08:02:13 +08:00
Nguyen Anh Quynh 55a6874a08 Merge pull request #428 from cseagle/bindings 
Bindings
 2016-02-08 10:15:19 +08:00
Chris Eagle 9b8098bf63 file perms 2016-02-07 07:24:34 -08:00
Chris Eagle 84fbe5aa5d add x86 mmr handling to java binding 2016-02-07 07:23:07 -08:00
Chris Eagle a5b1ae47c3 remove unnecessary file 2016-02-06 19:19:55 -08:00
Nguyen Anh Quynh 6cdd11e5d8 Merge pull request #427 from cseagle/bindings 
Bindings
 2016-02-07 08:58:50 +08:00
Chris Eagle ec5998bd02 fix file perms 2016-02-06 15:18:44 -08:00
Chris Eagle 21b9fa860b fix file perms 2016-02-06 15:18:03 -08:00
Chris Eagle aa1657006b implement missing APIs (uc_query, uc_mem_map_ptr, uc_mem_regions) in java binding 2016-02-06 15:16:44 -08:00
Nguyen Anh Quynh ca942c45a4 Merge pull request #426 from McLovi9/patch-3 
Add query mode bind
 2016-02-07 00:33:26 +08:00
McLovi9 7394a9ba30 Add query mode bind 2016-02-06 14:35:31 +01:00
Nguyen Anh Quynh 6986fa3947 x86: add new register enums for IDT, LDT, GDT & TR 2016-02-06 17:35:45 +08:00
Nguyen Anh Quynh ed77cacbf3 cosmetic change for uc_x86_mmr 2016-02-06 17:34:19 +08:00
Nguyen Anh Quynh 6478a24404 Merge branch 'gdt_idt' of https://github.com/cseagle/unicorn into cseagle-gdt_idt 2016-02-06 17:31:42 +08:00
Nguyen Anh Quynh e73cbf1c88 arm: UC_QUERY_MODE return hardware mode (see issue #397) 2016-02-06 09:47:57 +08:00
Nguyen Anh Quynh 49974cd395 Merge pull request #422 from cseagle/x86_seg_regs 
X86 seg regs
 2016-02-06 09:37:42 +08:00
Chris Eagle dec3615d12 ldtr and tr limit is 20 bits, not 16 bits 2016-02-04 19:26:47 -08:00
Chris Eagle b49358524f fix reg_read casting for x86 segment registers 2016-02-04 19:22:39 -08:00
Chris Eagle 4cb43be5bf fix reg_read casting for x86 segment registers 2016-02-04 19:20:59 -08:00
Chris Eagle 49b9f4f8da uc_x86_mmr type available in qemu/target-i386/unicorn.c 2016-02-04 19:09:41 -08:00
Nguyen Anh Quynh 07e8f2f60d Merge pull request #423 from lunixbochs/master 
add regress for #421
 2016-02-05 09:45:01 +08:00
Ryan Hileman bcfa41c90d add regress for #421 2016-02-05 02:35:17 +01:00
Chris Eagle c339ced218 file perms 2016-02-04 17:18:24 -08:00
Chris Eagle f3dc2522a0 read/write of x86 segment registers should modify selector field not base field 2016-02-04 17:17:40 -08:00
Nguyen Anh Quynh 9b6d1bf324 regress: fix compilation warning for mem_fuzz.c 2016-02-05 08:54:52 +08:00
Nguyen Anh Quynh a5d9daaef4 Merge branch 'mem_fuzzing' of https://github.com/eqv/unicorn into eqv-mem_fuzzing 2016-02-05 08:49:18 +08:00
Chris Eagle 59f7bf3be7 file perms 2016-02-04 16:48:27 -08:00
Chris Eagle e59382e030 updated gdtr/idtr/ldtr/tr read/write code 2016-02-04 16:44:52 -08:00
coco 1e13777c91 added memory fuzzer and 2 resulting testcases 2016-02-04 19:57:20 +01:00
Chris Eagle 9977054a15 add support for setting gdtr, idtr, ldtr, and tr programatically 2016-02-03 09:22:29 -08:00
Nguyen Anh Quynh 101f14285a chmod +x arm_init_input_crash.py 2016-02-03 09:20:15 +08:00
McLovi9 ac806d3bfb Create arm_init_input_crash.py 2016-02-02 20:36:36 +01:00
Nguyen Anh Quynh dad2baa92f Merge pull request #411 from cforger/master 
Fix sample_network_auditing.py so it works with Python3
 2016-02-01 10:42:30 +08:00
cforgeron de224f1573 - Switch to 'in' which works in 2/3 instead of legacy '.has_key()' 
- Renamed 'id' variable use (which is a built-in) to my_id.
- Small formatting changes to make it more PEP compliant.
 2016-01-31 17:01:14 -04:00
cforgeron 44fa4e29e7 - Added detect for Python 2/3 so the correct iteritems()/iter is called. 
- Renamed 'id' variable use (which is a built-in) to my_id.
- Small formatting changes to make it more PEP compliant.
 2016-01-31 15:09:20 -04:00
Nguyen Anh Quynh e42aba760f fix a typo in test_tb_x86.c 2016-01-31 14:07:35 +08:00
Nguyen Anh Quynh 32b9deca04 unit: use UC_HOOK_MEM_VALID for test_tb_x86.c 2016-01-31 13:14:11 +08:00
Nguyen Anh Quynh a2ef52172c add combination hook type UC_HOOK_MEM_VALID to intercept all valid memory access 2016-01-31 13:12:34 +08:00
Nguyen Anh Quynh 1fb5416f4a unit: simplify test_tb_x86.c 2016-01-31 13:06:42 +08:00
Nguyen Anh Quynh a5020c69bb Merge pull request #408 from egberts/master 
Pull Request for Issue #364: Invalidating Translation Cache after self-modifying code
 2016-01-31 10:37:04 +08:00
steve fc22a359e2 Issue #364 - Move RIP/PC closer next to the offending self-modifying code 
which modified the 2nd next instruction (imul) in which that escaped
our wonderful ability to invalidate the
instruction translation cache in which we badly need to pick up the
self-modification being made.
 2016-01-30 19:30:17 -05:00
Nguyen Anh Quynh c8569d8128 arm: fix change PC feature. now tests/regress/callback-pc.py passes 2016-01-28 16:03:19 +08:00
Nguyen Anh Quynh 5a04bcb115 allow to change PC during callback. this solves issue #210 2016-01-28 14:06:17 +08:00
Nguyen Anh Quynh e750a4e97c when uc_mem_exec() remove EXE permission, quit current TB & continue emulating with TB flushed. this fixes issue in PR #378 2016-01-28 00:56:55 +08:00
Nguyen Anh Quynh 876c423dd0 python: support recent change on uc_hook_add() with begin/end params 2016-01-26 23:12:35 +08:00
Nguyen Anh Quynh 48ab148d1c Merge branch 'hook' 2016-01-26 22:52:29 +08:00
Nguyen Anh Quynh 235bf0950b cosmetic change for mem_apis.c 2016-01-26 22:50:35 +08:00
Nguyen Anh Quynh 2341f5dd1a code style 2016-01-26 17:37:48 +08:00