Jonathon Reinhart
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4dae31b25e
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add uc_assert_(err|fail) macros
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2015-09-20 21:13:22 -04:00 |
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Jonathon Reinhart
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df3966a90c
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continued work on test framework
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2015-09-20 21:13:22 -04:00 |
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Jonathon Reinhart
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d4de54601d
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add start of test_mem_map.c
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2015-09-20 21:13:22 -04:00 |
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Jonathon Reinhart
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12909e6a4c
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add basic cmocka unit test
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2015-09-20 21:13:22 -04:00 |
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Nguyen Anh Quynh
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ad835459bd
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fix conflicts when merging new_regress to master
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2015-09-20 00:21:20 +07:00 |
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Nguyen Anh Quynh
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9aa04d9496
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tb_gen_code(): only check to link next page if tb->size > 0 (so we skip empty block)
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2015-09-20 00:05:17 +07:00 |
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Nguyen Anh Quynh
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7ab8d667fd
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fix regress/fpu_mem_write.py so it really emulates code
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2015-09-20 00:02:30 +07:00 |
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Nguyen Anh Quynh
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4d45f11a08
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regress/regress.py can be run from inside regress/
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2015-09-19 17:06:50 +07:00 |
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danghvu
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cbb2cf3618
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Regress python testcases must define expected value via unittest
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2015-09-17 15:45:15 -05:00 |
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danghvu
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8c163706e4
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Fix issue #113, untracked reference
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2015-09-16 21:33:01 -05:00 |
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Nguyen Anh Quynh
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5005b4a6e2
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arm: early check to see if the address of this block is the until address
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2015-09-17 09:16:57 +07:00 |
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Nguyen Anh Quynh
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d6b9c31dc9
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sparc: more cleanup
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2015-09-16 16:04:12 +07:00 |
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Nguyen Anh Quynh
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f36bd83f85
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cleanup regress/sparc*.py
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2015-09-16 15:46:10 +07:00 |
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mothran
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893e6abcbd
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first atttempt at SPARC64 fixes, no longer SEGV's, set CPU model to: Sun UltraSparc IV
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2015-09-15 23:12:03 -07:00 |
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Nguyen Anh Quynh
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fe807952d0
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bindings: update Sparc registers after the last core change
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2015-09-15 14:17:57 +07:00 |
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Nguyen Anh Quynh
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e581b8ea0e
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Merge branch 'master' of https://github.com/unicorn-engine/unicorn
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2015-09-15 14:17:10 +07:00 |
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Nguyen Anh Quynh
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7eaedc5c15
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add a comment for Arm instruction in regress/arm_movr12_hang.py
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2015-09-15 14:16:57 +07:00 |
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Nguyen Anh Quynh
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163e49bf59
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Merge pull request #141 from mothran/sparc_regs
Updated sparc register system
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2015-09-15 14:14:46 +07:00 |
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mothran
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6962126707
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update sparc_reg.py with %i registers
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2015-09-14 23:28:09 -07:00 |
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mothran
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d1e19df64e
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update the sparc_reg to test all g/o/l registers
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2015-09-14 23:05:33 -07:00 |
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mothran
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69d73aa845
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added emulated SPARC code for regress/sparc_reg.py, appears to be a bug in G and I registers
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2015-09-14 21:23:42 -07:00 |
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mothran
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1638372793
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fix small whitespace issue
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2015-09-14 20:48:31 -07:00 |
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mothran
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f4894a1c77
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removed unneed cases in the switch statement
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2015-09-14 20:44:50 -07:00 |
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mothran
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d4d5631181
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updated the sparc.h header so the alignment of certain registers was correct
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2015-09-14 20:42:41 -07:00 |
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mothran
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6b521e9e9b
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update the sparc reg read/write to include o/l/i registers
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2015-09-14 20:03:32 -07:00 |
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mothran
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85b3594c7c
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Merge branch 'master' of github.com:unicorn-engine/unicorn into sparc_regs
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2015-09-14 19:57:23 -07:00 |
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Nguyen Anh Quynh
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3f726d1c57
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chmod +x regress/sparc64.py
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2015-09-14 09:46:05 +07:00 |
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mothran
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7dc41a8e4e
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update the regwptr upon reset
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2015-09-13 18:10:28 -07:00 |
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Nguyen Anh Quynh
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507fc4dab7
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Merge pull request #137 from mothran/sparc64_crash
added the sparc64 crash regression
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2015-09-13 09:34:20 +08:00 |
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mothran
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2789e7951b
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added the sparc64 crash regression
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2015-09-12 10:35:50 -07:00 |
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mothran
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657a6c3e25
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modified the sparc reg get/set functions to use the current reg window ptr
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2015-09-12 10:29:35 -07:00 |
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mothran
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afecfee565
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added SPARC sp / fp registers, also updated uint32_t's to uint64_t's in SPARC64
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2015-09-10 23:20:52 -07:00 |
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Nguyen Anh Quynh
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548355acca
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sparc: do not accept BIGENDIAN mode in samples. more sanity check should be done in the core
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2015-09-11 14:02:27 +08:00 |
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Nguyen Anh Quynh
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b306fa65bd
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Merge pull request #135 from lunixbochs/test-133
add test for #133
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2015-09-10 01:17:15 +08:00 |
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Ryan Hileman
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586d5ca9f8
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add test for #133
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2015-09-09 08:27:13 -07:00 |
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Nguyen Anh Quynh
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113245e12a
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fix some comments in unicorn.h
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2015-09-09 17:00:00 +08:00 |
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Nguyen Anh Quynh
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39ac1bcb4e
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rename UC_ERR_INVAL to UC_ERR_ARG
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2015-09-09 16:54:47 +08:00 |
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Nguyen Anh Quynh
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d7ef204398
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rename error codes ERR_MEM_READ, ERR_MEM_WRITE, ERR_MEM_FETCH
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2015-09-09 16:25:48 +08:00 |
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Nguyen Anh Quynh
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d3d38d3f21
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handle read/write/fetch from unaligned addresses. this adds new error codes UC_ERR_READ_UNALIGNED, UC_ERR_WRITE_UNALIGNED & UC_ERR_FETCH_UNALIGNED
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2015-09-09 15:52:15 +08:00 |
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Nguyen Anh Quynh
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6b52be24a3
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fix regress/mips_except.py
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2015-09-09 15:32:31 +08:00 |
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Nguyen Anh Quynh
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18b6680e96
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mips: disable debug output
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2015-09-08 23:56:25 +08:00 |
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Nguyen Anh Quynh
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99379e92e9
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Merge pull request #131 from lunixbochs/mips-exception
add regress for #130
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2015-09-08 15:47:53 +08:00 |
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Ryan Hileman
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d134c62366
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add regress for #130
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2015-09-08 00:44:14 -07:00 |
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Nguyen Anh Quynh
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09c66f2183
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Merge pull request #129 from lunixbochs/master
refactor Go bindings to be more idiomatic
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2015-09-08 15:32:13 +08:00 |
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Ryan Hileman
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9a0d80b84c
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refactor Go bindings to be more idiomatic
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2015-09-08 00:04:27 -07:00 |
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Nguyen Anh Quynh
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fda17cd377
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java: rename UC_MEM_EXE to UC_MEM_FETCH
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2015-09-08 12:57:40 +08:00 |
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Nguyen Anh Quynh
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7a5d790ade
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rename UC_MEM_EXE to UC_MEM_FETCH
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2015-09-08 12:55:56 +08:00 |
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Nguyen Anh Quynh
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d9f4e3f56b
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Merge pull request #128 from lunixbochs/no-go-uc
go binding updates
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2015-09-08 11:14:29 +08:00 |
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Ryan Hileman
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7beb90ca95
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remove UC_ prefix for go binding consts
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2015-09-07 19:25:13 -07:00 |
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Ryan Hileman
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185b7a7cef
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fix Go types on uc_mem_read() and uc_mem_write()
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2015-09-07 19:25:04 -07:00 |
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