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470 Commits

Author SHA1 Message Date
Chen Huitao
23a426625f check arguments, return error instead of raising exceptions. (#1125) 
* check arguments, return error instaed of raising exceptions. close #1117.

* remove empty lines. remove thr underscore prefix in function name.
 2019-08-23 17:05:13 +08:00
Daniel Deptford
bc572be472 Check for TLB invalidation after read callback(s). (#1122) 
* Adding regression test for issue where writing memory into a read only segment during a access callback fails.

* Check for TLB invalidation when calling read callbacks;  Writes to read-only memory by the callback cause a TLB flush which requires a re-read of the TLB.
 2019-08-22 17:54:24 +08:00
naq
9208a6f317 initialize ret=0 in cpu_exec(). issue #1115 2019-08-05 23:00:01 +08:00
naq
540c893157 cleanup qemu/cpus.c 2019-07-31 15:43:06 +08:00
kj.xwings.l
24f55a7973 Removed hardcoded CP0C3_ULRI (#1098) 
* activate CP0C3_ULRI for CONFIG3, mips

* updated with mips patches

* updated with mips patches

* remove hardcoded config3

* git ignore vscode

* fix spacing issue and turn on floating point
 2019-07-06 17:53:02 +08:00
kj.xwings.l
5efc0afd49 activate CP0C3_ULRI for CONFIG3, mips (#1097) 2019-06-24 20:58:53 +08:00
Ryan Houdek
ae6e3c193d Fixes register reading and writing for XMM8-15 on x86-64 (#1090) 2019-06-03 19:04:41 +08:00
Lukas Dresel
55d8d073bd support for YMM registers ymm8-ymm15 (#1079) 2019-04-01 11:00:34 +08:00
yhql
3185128031 Add ARM MSP, PSP and CONTROL register access (#1071) 
Necessary for NVIC exception emulation from user.
 2019-03-07 08:37:27 +08:00
cfrantz
6c319941a5 Add support for the ARM IPSR register. (#1067) 
1. Create an enum name for the IPSR register.
2. Implement read and write of the IPSR via the xpsr helper functions.

Fixes #1065
 2019-02-28 09:55:27 +08:00
dmarxn
5bf6d77e4e Fixed the decoding of opcodes after getting vex2 using 0xc5 (#1064) 
* Fixed the decoding of opcodes after getting vex2 using 0xc5

* Added testcase for vex. Can and should be expanded

* Fixed warning of testcase for vex (parentheses for assignment)
 2019-02-25 21:14:20 +08:00
dmarxn
256e7782ce Added MXCSR register, fixed writing to FPUCW. (#1059) 
* Added MXCSR register for reading and writing

* Changed writing for fpucw register, now the qemu rounding status is updated as well
 2019-02-15 12:59:49 +08:00
dmarxn
360e9c60e1 changed cpu_compue_eflags to use the updated eflags variable. Otherwise, cli/sti and popfl may break, as we get the non-updated eflags (#1057) 2019-02-07 23:10:01 +08:00
dmarxn
3df5ef8ab1 Fixed conditional move tcg bug (tcg_gen_movcond), which generated an ALWAYS / NEVER condition despite QEMU no supporting those conditions in the tcg_out part (#1054) 2019-01-31 09:59:51 +08:00
BrunoPujos
536c4e77c4 i386: set MSR IA32_EFER to correct value at init for IA32e Mode (#1047) 2018-11-30 11:42:19 +08:00
nanoric
a2493a0d41 [Fix] Fix a problem that use uc_reg_write to write fs, gs has no effets in x86 64-bit mode. (#984) 2018-11-10 21:24:11 +08:00
Catena cyber
400a0ab309 Uses latest qemu arm thumb load store stuff (#1021) 2018-09-27 10:32:48 +08:00
Catena cyber
333bfdf65e Removes accessible assert (#1022) 2018-09-24 20:21:30 +08:00
Catena cyber
46999575fb Mips undefined shift fix (#1011) 2018-09-16 21:51:03 +08:00
Catena cyber
910999d396 Prevents abort with m68K (#1012) 
* Prevents abort with m68K

Raises exception instead

* M68K remove one uses of abort

* Less aborts and logs instead for M68K
 2018-09-16 21:50:35 +08:00
Catena cyber
4a86318cf4 Initializes i386 prefix value (#1013) 2018-09-16 21:50:00 +08:00
Catena cyber
b8df067514 Sparc increase ttl number (#1016) 2018-09-16 21:49:34 +08:00
Catena cyber
12bcf3bea0 Fuzz builds ok (#1007) 
* Fuzzing M68K without abort

* UC_MODE_32 is not ok with sparc

use UC_MODE_SPARC32|UC_MODE_BIG_ENDIAN instead

* Temporary removing leaking on start targets

* Do not abort for m68K undef instructions
 2018-09-11 12:49:32 +08:00
toshiMSFT
0f14c47344 Makes SYSENTER hookable again on x86 (#996) 
Adds SYSENTER to the whitelist of supported hookable instructions in unicorn
as well as fixes up the existing sysenter_hook_x86 regression test which was
previously failing

Fixes unicorn-engine/unicorn#995
 2018-08-09 23:32:31 +08:00
Alex von Gluck IV
c7be4a2160 Haiku support patches (#989) 
* Haiku: fix broken gcc strong stack protector

* qemu: Backport minor Haiku fix

We need to push this fix upstream to qemu. If we don't
get it upstreamed, i'll circle back and patch it if
Unicorn updates its qemu version.
 2018-08-03 11:15:14 +08:00
Nguyen Anh Quynh
4d0157eb4a x86: fix #968. also fix potential bug of not clearing high bytes when updateing EIP 2018-07-26 15:19:23 +08:00
Nguyen Anh Quynh
86313650f9 fix some gcc warnings 2018-07-25 12:38:15 +08:00
nanoric
2a240079d8 [Fix] Add feature support for CMPXCHG16B instruction. (#983) 2018-07-25 15:00:41 +08:00
Nguyen Anh Quynh
d5f83a9c2e arm: cleanup for ARM_CPU 2017-12-21 09:43:33 +08:00
Nguyen Anh Quynh
e67be36c88 arm: remove unused variable in arm_cpu_get_phys_page_debug() 2017-12-20 22:12:35 +08:00
Nguyen Anh Quynh
3e0d0cfab7 i386: fix signed int overflow in #923 & #924 2017-12-16 10:28:45 +08:00
Andrew Dutcher
d7735487f7 Use the qemu helpers to get/set the x86 eflags (#878) 2017-09-15 22:18:38 +07:00
Andrew Dutcher
363cbacee4 Only set eip to the instruction pointer after an interrupt if the interrupt was user-generated (#875) 2017-08-29 17:14:36 +07:00
darkf
42d0632108 Fix typo in ARM tcg-target.c (#859) 2017-07-22 23:36:38 +08:00
vardyh
ad767abda8 x86::trans: handle illegal case for opc c6/c7 
Reference Intel software developer manual vol2 Appendix A Table A-6 for
detailed decoding information.

Signed-off-by: vardyh <vardyh.dev@gmail.com>
 2017-05-25 15:22:45 +08:00
misson20000
014ccfb94a Aarch64 add thread registers (#834) 
* add thread registers to AArch64

* update bindings to add AArch64 thread registers

* fix indentation for register read/write switch-case in unicorn_aarch64.c
 2017-05-14 14:42:49 +07:00
bulaza
4b9efdc986 Adding INSN hook checks for x86 (#833) 
* adding INSN hook checking for x86

* tabs to spaces

* need to return bool not uc_err

* fixed conditional after switching to bool
 2017-05-14 00:16:17 +07:00
Ryan Hileman
ae6ea3b91d fix arm64 hang (fix #827) (#828) 2017-05-09 20:19:32 +08:00
Samuel Groß
5385baba39 Implemented read and write access to the YMM registers (#819) 2017-05-05 09:02:58 +08:00
zhangwm
4a62409949 arm64eb: arm64 big endian also using little endian instructions. (#816) 
* arm64eb: arm64 big endian also using little endian instructions.

* arm64: using another example that depends on endians.

example:
1. store a word: 0x12345678
2. load a byte:
   * little endian : 0x78
   * big endian    : 0x12
 2017-05-04 20:00:48 +08:00
Ryan Hileman
1b00d3f89a remove slow cpu QOM casts (#815) 2017-05-02 14:56:39 +08:00
Ryan Hileman
187b470245 add arm64 CPACR_EL1 register support (#814) 2017-05-02 14:51:19 +08:00
zhangwm
2e973a13f0 arm64eb: add support for ARM64 big endian. 2017-04-24 23:30:01 +08:00
Nguyen Anh Quynh
513075e061 arm: fix an warning reported by GCC 2017-04-21 21:12:57 +08:00
Nguyen Anh Quynh
e917c9de10 Merge branch 'master' into msvc2 2017-04-21 01:17:00 +08:00
0xSeb
605400e10e determine correct Thumb/Thumb2 instruction size (16/32-bit) for code … (#796) 
* determine correct Thumb/Thumb2 instruction size (16/32-bit) for code hook

* determine correct Thumb/Thumb2 instruction size (16/32-bit) for code hook

* determine correct Thumb/Thumb2 instruction size (16/32-bit) for code hook
 2017-04-15 00:39:56 +08:00
Nguyen Anh Quynh
f915f14e74 Merge branch 'master' of https://github.com/unicorn-engine/unicorn 2017-04-12 22:06:40 +08:00
Nguyen Anh Quynh
cb44f77ac3 mips: fix uc_reg_read() for MIPS64 2017-04-12 22:06:26 +08:00
Nguyen Anh Quynh
3315f288d3 fix an warning in glib_compat.c 2017-04-12 14:01:58 +08:00
bunnei
4eca426fb6 unicorn_aarch64: Expose UC_ARM64_REG_NZCV register. (#791) 2017-03-31 10:21:45 +08:00