Added MXCSR register, fixed writing to FPUCW. (#1059)
* Added MXCSR register for reading and writing * Changed writing for fpucw register, now the qemu rounding status is updated as well
This commit is contained in:
parent
360e9c60e1
commit
256e7782ce
|
@ -88,7 +88,7 @@ typedef enum uc_x86_reg {
|
|||
UC_X86_REG_IDTR, UC_X86_REG_GDTR, UC_X86_REG_LDTR, UC_X86_REG_TR, UC_X86_REG_FPCW,
|
||||
UC_X86_REG_FPTAG,
|
||||
UC_X86_REG_MSR, // Model-Specific Register
|
||||
|
||||
UC_X86_REG_MXCSR,
|
||||
UC_X86_REG_ENDING // <-- mark the end of the list of registers
|
||||
} uc_x86_reg;
|
||||
|
||||
|
|
|
@ -471,6 +471,9 @@ int x86_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int coun
|
|||
case UC_X86_REG_MSR:
|
||||
x86_msr_read(uc, (uc_x86_msr *)value);
|
||||
break;
|
||||
case UC_X86_REG_MXCSR:
|
||||
*(uint32_t *)value = X86_CPU(uc, mycpu)->env.mxcsr;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
|
@ -753,6 +756,9 @@ int x86_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int coun
|
|||
case UC_X86_REG_MSR:
|
||||
x86_msr_read(uc, (uc_x86_msr *)value);
|
||||
break;
|
||||
case UC_X86_REG_MXCSR:
|
||||
*(uint32_t *)value = X86_CPU(uc, mycpu)->env.mxcsr;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
#endif
|
||||
|
@ -795,7 +801,7 @@ int x86_reg_write(struct uc_struct *uc, unsigned int *regs, void *const *vals, i
|
|||
}
|
||||
continue;
|
||||
case UC_X86_REG_FPCW:
|
||||
X86_CPU(uc, mycpu)->env.fpuc = *(uint16_t *)value;
|
||||
cpu_set_fpuc(&X86_CPU(uc, mycpu)->env, *(uint16_t *)value);
|
||||
continue;
|
||||
case UC_X86_REG_FPTAG:
|
||||
{
|
||||
|
@ -1018,6 +1024,9 @@ int x86_reg_write(struct uc_struct *uc, unsigned int *regs, void *const *vals, i
|
|||
case UC_X86_REG_MSR:
|
||||
x86_msr_write(uc, (uc_x86_msr *)value);
|
||||
break;
|
||||
case UC_X86_REG_MXCSR:
|
||||
cpu_set_mxcsr(&X86_CPU(uc, mycpu)->env, *(uint32_t *)value);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
|
@ -1310,6 +1319,9 @@ int x86_reg_write(struct uc_struct *uc, unsigned int *regs, void *const *vals, i
|
|||
case UC_X86_REG_MSR:
|
||||
x86_msr_write(uc, (uc_x86_msr *)value);
|
||||
break;
|
||||
case UC_X86_REG_MXCSR:
|
||||
cpu_set_mxcsr(&X86_CPU(uc, mycpu)->env, *(uint32_t *)value);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
#endif
|
||||
|
|
Loading…
Reference in New Issue