Nguyen Anh Quynh
0680b85920
cleanup Monitor related code
2017-01-23 10:07:01 +08:00
Nguyen Anh Quynh
81b8a685be
cleanup
2017-01-23 10:06:49 +08:00
xorstream
e46f86c80b
Merging with current msvc.
2017-01-23 01:07:06 +11:00
xorstream
72a497bc14
Added MIPS support and projects for all samples.
2017-01-23 01:05:08 +11:00
Nguyen Anh Quynh
206819bd98
cleanup after msvc port
2017-01-22 21:27:17 +08:00
xorstream
770c5616e2
Automated leading tab to spaces conversion.
2017-01-21 12:28:22 +11:00
xorstream
b0ae2138fb
Merge remote-tracking branch 'unicorn-engine/master' into msvc_native
2017-01-20 22:37:51 +11:00
Nguyen Anh Quynh
fff532fc20
timer is redundant
2017-01-20 16:46:58 +08:00
xorstream
92392e0f57
Merge with current master.
2017-01-20 18:22:28 +11:00
xorstream
002151874a
Unicorn interface working with test app in 32bit and 64bit builds.
2017-01-20 17:27:22 +11:00
xorstream
1aeaf5c40d
This code should now build the x86_x64-softmmu part 2.
2017-01-19 22:50:28 +11:00
Nguyen Anh Quynh
8a5b12c6f9
more cleanup in qemu/include/hw/
2017-01-19 15:20:06 +08:00
Nguyen Anh Quynh
7789a06d2d
cleanup qemu/default-configs/
2017-01-19 14:52:30 +08:00
Nguyen Anh Quynh
0640b35943
mips: remove qemu/hw/mips/mips_int.c
2017-01-19 13:07:28 +08:00
Nguyen Anh Quynh
a154b251e3
cleanup
2017-01-19 12:18:46 +08:00
cojocar
428cb83060
Support for MCLASS ARM cpu (Cortex-M3) ( #700 )
...
Support for Cortex-M ARM CPU already exists in Qemu. This patch just
exposes a "cortex-m3" CPU.
"uc_open(UC_ARCH_ARM, UC_MODE_THUMB | UC_MODE_MCLASS, &uc);"
Instantiates a CPU with this feature on.
Signed-off-by: Lucian Cojocar <lucian@cojocar.com>
2016-12-27 22:49:06 +08:00
Nguyen Anh Quynh
1f65b76fbd
fix some compilation warnings regarding typcase of (CPUState *)
2016-10-26 17:05:26 +08:00
Nguyen Anh Quynh
2a608c778e
sparc: fix an compilation warning
2016-10-21 22:32:02 +08:00
danghvu
84d99412bc
memleak: Fix Sparc memory leak
2016-10-03 14:23:27 -05:00
Ryan Hileman
cb615fdba7
remove uc->cpus
2016-09-23 07:38:21 -07:00
Nguyen Anh Quynh
c61aff1dbe
mips: remove an unused variable
2016-07-15 15:12:15 +08:00
danghvu
27e0699ef5
mips: Fix memleak
2016-07-09 20:16:00 -05:00
Nguyen Anh Quynh
3a742fb6f6
fix conflicts when merging no-thread to master
2016-04-23 10:06:57 +08:00
Chris Eagle
9467254fc0
strip out per cpu thread code
2016-03-25 17:24:28 -07:00
danghvu
36e53ad8a1
Fix arm & arm64 memleaks
2016-01-31 16:22:20 -06:00
Nguyen Anh Quynh
2f297bdd3a
handle some errors properly so avoid exit() during initialization. this fixes issue #237
2015-11-12 01:43:41 +08:00
Nguyen Anh Quynh
d6b9c31dc9
sparc: more cleanup
2015-09-16 16:04:12 +07:00
mothran
893e6abcbd
first atttempt at SPARC64 fixes, no longer SEGV's, set CPU model to: Sun UltraSparc IV
2015-09-15 23:12:03 -07:00
Nguyen Anh Quynh
18b6680e96
mips: disable debug output
2015-09-08 23:56:25 +08:00
Nguyen Anh Quynh
6c132bc673
arm: fix #114 by enabling cortex-a15 model. FIXME: enable this on demand with an API
2015-09-08 01:08:37 +08:00
Nguyen Anh Quynh
344d016104
import
2015-08-21 15:04:50 +08:00
