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134 Commits

Author SHA1 Message Date
mio db9ddabf9e
Update bindings 2022-11-01 10:06:34 +01:00
TSR Berry 7b8b75b9f8
bindings: Adjust consts 2022-10-14 17:33:07 +02:00
TSR Berry c787fa8e64
bindings: Update Arm64 consts 2022-10-14 15:18:16 +02:00
Nguyen Anh Quynh 1ec1352995 bindings: update consts 2022-07-07 23:48:01 +08:00
Mio af1c661a12
Update bindings 2022-07-06 09:33:45 +08:00
Eric Poole cfee2139a0
TriCore Support (#1568) 
* TriCore Support

python sample

* Update sample_tricore.py

Correct attribution

* Update sample_tricore.py

Fixed byte code to execute properly.

* Update sample_tricore.py

Removed testing artifact

* Added tricore msvc config-file.h

* Added STATIC to tricore config and added helper methods to symbol file generation.

* Update op_helper.c

Use built in crc32

* Fix tricore samples and small code blocks are now handled properly

* Add CPU types

* Generate bindings

* Format code

Co-authored-by: lazymio <mio@lazym.io>
 2022-04-29 23:11:34 +02:00
lazymio cdae57fb3d
Generate bindings 2022-04-26 01:17:58 +02:00
lazymio 185a6fec9e
Bump bindings version to 2.0.0-rc7 2022-04-17 16:48:12 +02:00
lazymio 5a79d7879c
Generate bindings 2022-04-16 17:50:32 +02:00
Ilya Leoshkevich 28c4c665f0 Add "holes" to where the removed x86 registers used to be 
A number of x86 registers were removed for #1440, causing a change in
numbering for many other registers. This is causing inconveniences at
the moment, e.g. it's not possible to use the Unicorn2 shared library
as a drop-in replacement for the Unicorn1 one.

Restore the old numbering.

Fixes #1492.
 2022-03-22 11:31:58 +01:00
lazymio dd96cab9bf
Update bindings 2022-02-27 15:28:32 +01:00
Bet4 504b31b928 Update constants of bindings 2022-02-19 21:24:40 +08:00
lazymio 3ed9dbda13
Update bindings 2022-02-15 22:08:27 +01:00
lazymio c10639fd46
Bump version in bindings 2022-02-13 11:03:57 +01:00
lazymio 89a1da9a33
Update bindings 2022-02-11 22:42:31 +01:00
mio f57467e7ed
Generate bindings 2022-01-19 20:10:09 +01:00
lazymio 459a595a98
Merge branch 'dev' into s390x 
Mostly for bindings update.
 2022-01-15 20:56:39 +01:00
lazymio dfb0446137
Update bindings 2022-01-15 20:56:24 +01:00
lazymio 71f044ca50
Merge branch 'dev' into s390x 2022-01-10 15:17:42 +01:00
lazymio c671efe798
Update bindings 2022-01-05 22:00:59 +01:00
lazymio c4b4189857
Update bindings 2022-01-04 21:12:52 +01:00
Nguyen Anh Quynh 6813e4a042 bindings: update const_generator.py, and update all binding constants 2022-01-01 09:24:28 +08:00
Brandon Miller 2cc15c7260 Added SetCPUModel go binding 
Go cannot use C macros directly, so I followed existing convention and
added a helper to uc.c to call the uc_ctl_set_cpu_model macro
 2021-12-04 16:25:23 -05:00
George Hotz 8732cff287
add rpath and go.mod 2021-11-07 20:24:50 +01:00
lazymio b9c0066a47
Format and naming 2021-11-04 20:04:57 +01:00
lazymio db90f39ac6
Generate bindings 2021-11-04 20:01:19 +01:00
lazymio 090686f8ed
uc_ctl proposal (#1473) 
* Add uc_ctl

* Add comments

* Slightly changed for bindings generation

* Generate bindings
 2021-10-30 10:45:32 +08:00
lazymio 9e1443013b
Fix gen_const 2021-10-26 13:10:59 +02:00
lazymio e695686c15
Remove AFL Integration by reverting 2021-10-26 11:22:21 +02:00
lazymio f08b7d6b5b
Make gen_const work and updates constants 2021-10-25 00:57:32 +02:00
Nguyen Anh Quynh e8bd7ca087 bindings: update X86 register constants 2021-10-04 19:41:41 +08:00
Nguyen Anh Quynh 0a7223996d bindings: update constants from ARM registers 2021-10-04 01:04:43 +08:00
Nguyen Anh Quynh aaaea14214 import Unicorn2 2021-10-03 22:14:44 +08:00
Nguyen Anh Quynh 2874435d2f bump version to 1.0.3 2021-05-16 21:38:08 +08:00
w4kfu-synacktiv 21ec6e8f83
Add ARM BE8 support (#1369) 
Co-authored-by: w4kfu <gw4kfu@gmail.com>
 2021-03-31 21:22:35 +08:00
Nguyen Anh Quynh fbef45b18f remove UC_ERR_TIMEOUT, so timeout on uc_emu_start() is not considered error. added UC_QUERY_TIMEOUT to query exit reason 2020-05-24 23:54:45 +08:00
Nguyen Anh Quynh cf3451c37a bindings: update ARM64 registers 2020-05-10 21:51:14 +08:00
Dominik Maier 625399774c
X64 base regs (#1166) 
* x86: setup FS & GS base

* Fixed base register writes for x64, removed then for x16/x32 (the don't exist there?)

* FS reg comes before GS so the base regs do so, too

* added shebang to const_generator.py

* Added base regs to and added 'all' support to const_generator

Co-authored-by: naq <aquynh@gmail.com>
 2020-05-05 08:34:51 +08:00
Nguyen Anh Quynh b0d5837c61 bindings: add UC_ERR_TIMEOUT 2019-12-29 00:19:34 +08:00
naq 3b17db0d84 bindings: update after the last commit on adding ARM modes 2019-10-26 05:02:39 +08:00
naq 355eaecc12 bindings: update after addition of UC_HOOK_INSN_INVALID 2019-09-23 01:54:24 +08:00
kj.xwings.l 24f55a7973 Removed hardcoded CP0C3_ULRI (#1098) 
* activate CP0C3_ULRI for CONFIG3, mips

* updated with mips patches

* updated with mips patches

* remove hardcoded config3

* git ignore vscode

* fix spacing issue and turn on floating point
 2019-07-06 17:53:02 +08:00
Jonas d6d4131873 Added x86Msr functions for the go bindings (#986) 2019-03-07 08:39:38 +08:00
Nguyen Anh Quynh 07cafff76a bindings: update for latest ARM registers addition 2019-03-07 08:38:41 +08:00
Nguyen Anh Quynh 6d47b38b7f bindings: update after recent addition of ARM_REG_IPSR 2019-02-28 09:56:29 +08:00
Nguyen Anh Quynh 738d102989 bindings: add newly added register MXCSR 2019-02-15 13:01:27 +08:00
Sebastian Willenborg 9a01ae8379 Fix tests when using go 1.10 (#949) 2018-03-21 00:36:37 +08:00
Nguyen Anh Quynh 41cc047b87 bindings: update after #922 2017-12-20 22:13:29 +08:00
misson20000 3fdb2d2442 add architecture query (#842) 2017-05-21 09:47:02 +08:00
misson20000 014ccfb94a Aarch64 add thread registers (#834) 
* add thread registers to AArch64

* update bindings to add AArch64 thread registers

* fix indentation for register read/write switch-case in unicorn_aarch64.c
 2017-05-14 14:42:49 +07:00