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Add ARM BE8 support (#1369)

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Co-authored-by: w4kfu <gw4kfu@gmail.com>
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w4kfu-synacktiv 2021-03-31 15:22:35 +02:00 committed by GitHub
parent 4440310f14
commit 21ec6e8f83
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GPG Key ID: 4AEE18F83AFDEB23
10 changed files with 16 additions and 2 deletions
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1
bindings/dotnet/UnicornManaged/Const/Common.fs
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@ -34,6 +34,7 @@ module Common =
let UC_MODE_ARM926 = 128
let UC_MODE_ARM946 = 256
let UC_MODE_ARM1176 = 512
let UC_MODE_ARMBE8 = 1024
let UC_MODE_MICRO = 16
let UC_MODE_MIPS3 = 32
let UC_MODE_MIPS32R6 = 64

1
bindings/go/unicorn/unicorn_const.go
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@ -29,6 +29,7 @@ const (
MODE_ARM926 = 128
MODE_ARM946 = 256
MODE_ARM1176 = 512
MODE_ARMBE8 = 1024
MODE_MICRO = 16
MODE_MIPS3 = 32
MODE_MIPS32R6 = 64

1
bindings/java/unicorn/UnicornConst.java
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@ -31,6 +31,7 @@ public interface UnicornConst {
public static final int UC_MODE_ARM926 = 128;
public static final int UC_MODE_ARM946 = 256;
public static final int UC_MODE_ARM1176 = 512;
public static final int UC_MODE_ARMBE8 = 1024;
public static final int UC_MODE_MICRO = 16;
public static final int UC_MODE_MIPS3 = 32;
public static final int UC_MODE_MIPS32R6 = 64;

1
bindings/pascal/unicorn/UnicornConst.pas
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@ -32,6 +32,7 @@ const UC_API_MAJOR = 1;
UC_MODE_ARM926 = 128;
UC_MODE_ARM946 = 256;
UC_MODE_ARM1176 = 512;
UC_MODE_ARMBE8 = 1024;
UC_MODE_MICRO = 16;
UC_MODE_MIPS3 = 32;
UC_MODE_MIPS32R6 = 64;

1
bindings/python/unicorn/unicorn_const.py
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@ -27,6 +27,7 @@ UC_MODE_V8 = 64
UC_MODE_ARM926 = 128
UC_MODE_ARM946 = 256
UC_MODE_ARM1176 = 512
UC_MODE_ARMBE8 = 1024
UC_MODE_MICRO = 16
UC_MODE_MIPS3 = 32
UC_MODE_MIPS32R6 = 64

1
bindings/ruby/unicorn_gem/lib/unicorn_engine/unicorn_const.rb
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@ -29,6 +29,7 @@ module UnicornEngine
UC_MODE_ARM926 = 128
UC_MODE_ARM946 = 256
UC_MODE_ARM1176 = 512
UC_MODE_ARMBE8 = 1024
UC_MODE_MICRO = 16
UC_MODE_MIPS3 = 32
UC_MODE_MIPS32R6 = 64

3
include/uc_priv.h
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@ -14,7 +14,7 @@
// These are masks of supported modes for each cpu/arch.
// They should be updated when changes are made to the uc_mode enum typedef.
#define UC_MODE_ARM_MASK (UC_MODE_ARM|UC_MODE_THUMB|UC_MODE_LITTLE_ENDIAN|UC_MODE_MCLASS \
|UC_MODE_ARM926|UC_MODE_ARM946|UC_MODE_ARM1176|UC_MODE_BIG_ENDIAN)
|UC_MODE_ARM926|UC_MODE_ARM946|UC_MODE_ARM1176|UC_MODE_BIG_ENDIAN|UC_MODE_ARMBE8)
#define UC_MODE_MIPS_MASK (UC_MODE_MIPS32|UC_MODE_MIPS64|UC_MODE_LITTLE_ENDIAN|UC_MODE_BIG_ENDIAN)
#define UC_MODE_X86_MASK (UC_MODE_16|UC_MODE_32|UC_MODE_64|UC_MODE_LITTLE_ENDIAN)
#define UC_MODE_PPC_MASK (UC_MODE_PPC64|UC_MODE_BIG_ENDIAN)
@ -239,6 +239,7 @@ struct uc_struct {
uint64_t addr_end; // address where emulation stops (@end param of uc_emu_start())
int thumb; // thumb mode for ARM
int bswap_code; // For mixed endian mode
// full TCG cache leads to middle-block break in the last translation?
bool block_full;
int size_arg; // what tcg arg slot do we need to update with the size of the block?

3
include/unicorn/unicorn.h
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@ -114,6 +114,9 @@ typedef enum uc_mode {
UC_MODE_ARM946 = 1 << 8, // ARM946 CPU type
UC_MODE_ARM1176 = 1 << 9, // ARM1176 CPU type
// ARM BE8
UC_MODE_ARMBE8 = 1 << 10, // Big-endian data and Little-endian code
// mips
UC_MODE_MICRO = 1 << 4, // MicroMips mode (currently unsupported)
UC_MODE_MIPS3 = 1 << 5, // Mips III ISA (currently unsupported)

2
qemu/target-arm/cpu.c
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@ -169,6 +169,8 @@ static void arm_cpu_reset(CPUState *s)
// Unicorn: force Thumb mode by setting of uc_open()
env->thumb = env->uc->thumb;
env->bswap_code = env->uc->bswap_code;
if (env->cp15.c1_sys & SCTLR_V) {
env->regs[15] = 0xFFFF0000;
}

4
uc.c
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@ -192,7 +192,9 @@ uc_err uc_open(uc_arch arch, uc_mode mode, uc_engine **result)
free(uc);
return UC_ERR_MODE;
}
if (mode & UC_MODE_BIG_ENDIAN) {
if (mode & (UC_MODE_BIG_ENDIAN | UC_MODE_ARMBE8)) {
if (mode & UC_MODE_ARMBE8)
uc->bswap_code = 1;
#ifdef UNICORN_HAS_ARMEB
uc->init_arch = armeb_uc_init;
#else