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Merge pull request #1722 from TSRBerry/dev 

aarch64: Add FPCR and FPSR registers
This commit is contained in:
lazymio 2022-10-15 00:17:38 +02:00 committed by GitHub
parent b99ec09c90 7b8b75b9f8
commit df3aa0fccb
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GPG Key ID: 4AEE18F83AFDEB23
8 changed files with 46 additions and 6 deletions
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6
bindings/dotnet/UnicornManaged/Const/Arm64.fs
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@ -318,7 +318,11 @@ module Arm64 =
let UC_ARM64_REG_VBAR_EL2 = 288 let UC_ARM64_REG_VBAR_EL2 = 288
let UC_ARM64_REG_VBAR_EL3 = 289 let UC_ARM64_REG_VBAR_EL3 = 289
let UC_ARM64_REG_CP_REG = 290 let UC_ARM64_REG_CP_REG = 290
let UC_ARM64_REG_ENDING = 291
// floating point control and status registers
let UC_ARM64_REG_FPCR = 291
let UC_ARM64_REG_FPSR = 292
let UC_ARM64_REG_ENDING = 293
// alias registers // alias registers
let UC_ARM64_REG_IP0 = 215 let UC_ARM64_REG_IP0 = 215

6
bindings/go/unicorn/arm64_const.go
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@ -313,7 +313,11 @@ const (
ARM64_REG_VBAR_EL2 = 288 ARM64_REG_VBAR_EL2 = 288
ARM64_REG_VBAR_EL3 = 289 ARM64_REG_VBAR_EL3 = 289
ARM64_REG_CP_REG = 290 ARM64_REG_CP_REG = 290
ARM64_REG_ENDING = 291
// floating point control and status registers
ARM64_REG_FPCR = 291
ARM64_REG_FPSR = 292
ARM64_REG_ENDING = 293
// alias registers // alias registers
ARM64_REG_IP0 = 215 ARM64_REG_IP0 = 215

6
bindings/java/unicorn/Arm64Const.java
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@ -315,7 +315,11 @@ public interface Arm64Const {
public static final int UC_ARM64_REG_VBAR_EL2 = 288; public static final int UC_ARM64_REG_VBAR_EL2 = 288;
public static final int UC_ARM64_REG_VBAR_EL3 = 289; public static final int UC_ARM64_REG_VBAR_EL3 = 289;
public static final int UC_ARM64_REG_CP_REG = 290; public static final int UC_ARM64_REG_CP_REG = 290;
public static final int UC_ARM64_REG_ENDING = 291;
// floating point control and status registers
public static final int UC_ARM64_REG_FPCR = 291;
public static final int UC_ARM64_REG_FPSR = 292;
public static final int UC_ARM64_REG_ENDING = 293;
// alias registers // alias registers
public static final int UC_ARM64_REG_IP0 = 215; public static final int UC_ARM64_REG_IP0 = 215;

6
bindings/pascal/unicorn/Arm64Const.pas
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@ -316,7 +316,11 @@ const
UC_ARM64_REG_VBAR_EL2 = 288; UC_ARM64_REG_VBAR_EL2 = 288;
UC_ARM64_REG_VBAR_EL3 = 289; UC_ARM64_REG_VBAR_EL3 = 289;
UC_ARM64_REG_CP_REG = 290; UC_ARM64_REG_CP_REG = 290;
UC_ARM64_REG_ENDING = 291;
// floating point control and status registers
UC_ARM64_REG_FPCR = 291;
UC_ARM64_REG_FPSR = 292;
UC_ARM64_REG_ENDING = 293;
// alias registers // alias registers
UC_ARM64_REG_IP0 = 215; UC_ARM64_REG_IP0 = 215;

6
bindings/python/unicorn/arm64_const.py
View File

@ -311,7 +311,11 @@ UC_ARM64_REG_VBAR_EL1 = 287
UC_ARM64_REG_VBAR_EL2 = 288 UC_ARM64_REG_VBAR_EL2 = 288
UC_ARM64_REG_VBAR_EL3 = 289 UC_ARM64_REG_VBAR_EL3 = 289
UC_ARM64_REG_CP_REG = 290 UC_ARM64_REG_CP_REG = 290
UC_ARM64_REG_ENDING = 291
# floating point control and status registers
UC_ARM64_REG_FPCR = 291
UC_ARM64_REG_FPSR = 292
UC_ARM64_REG_ENDING = 293
# alias registers # alias registers
UC_ARM64_REG_IP0 = 215 UC_ARM64_REG_IP0 = 215

6
bindings/ruby/unicorn_gem/lib/unicorn_engine/arm64_const.rb
View File

@ -313,7 +313,11 @@ module UnicornEngine
UC_ARM64_REG_VBAR_EL2 = 288 UC_ARM64_REG_VBAR_EL2 = 288
UC_ARM64_REG_VBAR_EL3 = 289 UC_ARM64_REG_VBAR_EL3 = 289
UC_ARM64_REG_CP_REG = 290 UC_ARM64_REG_CP_REG = 290
UC_ARM64_REG_ENDING = 291
# floating point control and status registers
UC_ARM64_REG_FPCR = 291
UC_ARM64_REG_FPSR = 292
UC_ARM64_REG_ENDING = 293
# alias registers # alias registers
UC_ARM64_REG_IP0 = 215 UC_ARM64_REG_IP0 = 215

4
include/unicorn/arm64.h
View File

@ -350,6 +350,10 @@ typedef enum uc_arm64_reg {
UC_ARM64_REG_CP_REG, UC_ARM64_REG_CP_REG,
//> floating point control and status registers
UC_ARM64_REG_FPCR,
UC_ARM64_REG_FPSR,
UC_ARM64_REG_ENDING, // <-- mark the end of the list of registers UC_ARM64_REG_ENDING, // <-- mark the end of the list of registers
//> alias registers //> alias registers

12
qemu/target/arm/unicorn_aarch64.c
View File

@ -225,6 +225,12 @@ static uc_err reg_read(CPUARMState *env, unsigned int regid, void *value)
case UC_ARM64_REG_CP_REG: case UC_ARM64_REG_CP_REG:
ret = read_cp_reg(env, (uc_arm64_cp_reg *)value); ret = read_cp_reg(env, (uc_arm64_cp_reg *)value);
break; break;
case UC_ARM64_REG_FPCR:
*(uint32_t *)value = vfp_get_fpcr(env);
break;
case UC_ARM64_REG_FPSR:
*(uint32_t *)value = vfp_get_fpsr(env);
break;
} }
} }
@ -318,6 +324,12 @@ static uc_err reg_write(CPUARMState *env, unsigned int regid, const void *value)
case UC_ARM64_REG_CP_REG: case UC_ARM64_REG_CP_REG:
ret = write_cp_reg(env, (uc_arm64_cp_reg *)value); ret = write_cp_reg(env, (uc_arm64_cp_reg *)value);
break; break;
case UC_ARM64_REG_FPCR:
vfp_set_fpcr(env, *(uint32_t *)value);
break;
case UC_ARM64_REG_FPSR:
vfp_set_fpsr(env, *(uint32_t *)value);
break;
} }
} }