From 12fd4fc086d78350e58a4f893aa8607f85d27580 Mon Sep 17 00:00:00 2001 From: TSR Berry <20988865+TSRBerry@users.noreply.github.com> Date: Fri, 14 Oct 2022 15:15:48 +0200 Subject: [PATCH 1/4] aarch64: Add FPCR and FPSR registers Co-authored-by: merry --- include/unicorn/arm64.h | 4 ++++ qemu/target/arm/unicorn_aarch64.c | 12 ++++++++++++ 2 files changed, 16 insertions(+) diff --git a/include/unicorn/arm64.h b/include/unicorn/arm64.h index 933be479..aab2ab9c 100644 --- a/include/unicorn/arm64.h +++ b/include/unicorn/arm64.h @@ -313,6 +313,10 @@ typedef enum uc_arm64_reg { UC_ARM64_REG_PSTATE, + //> floating point control and status registers + UC_ARM64_REG_FPCR, + UC_ARM64_REG_FPSR, + //> exception link registers, depreciated, use UC_ARM64_REG_CP_REG instead UC_ARM64_REG_ELR_EL0, UC_ARM64_REG_ELR_EL1, diff --git a/qemu/target/arm/unicorn_aarch64.c b/qemu/target/arm/unicorn_aarch64.c index f24c9506..4b533047 100644 --- a/qemu/target/arm/unicorn_aarch64.c +++ b/qemu/target/arm/unicorn_aarch64.c @@ -210,6 +210,12 @@ static uc_err reg_read(CPUARMState *env, unsigned int regid, void *value) case UC_ARM64_REG_PSTATE: *(uint32_t *)value = pstate_read(env); break; + case UC_ARM64_REG_FPCR: + *(uint32_t *)value = vfp_get_fpcr(env); + break; + case UC_ARM64_REG_FPSR: + *(uint32_t *)value = vfp_get_fpsr(env); + break; case UC_ARM64_REG_TTBR0_EL1: *(uint64_t *)value = env->cp15.ttbr0_el[1]; break; @@ -303,6 +309,12 @@ static uc_err reg_write(CPUARMState *env, unsigned int regid, const void *value) case UC_ARM64_REG_PSTATE: pstate_write(env, *(uint32_t *)value); break; + case UC_ARM64_REG_FPCR: + vfp_set_fpcr(env, *(uint32_t *)value); + break; + case UC_ARM64_REG_FPSR: + vfp_set_fpsr(env, *(uint32_t *)value); + break; case UC_ARM64_REG_TTBR0_EL1: env->cp15.ttbr0_el[1] = *(uint64_t *)value; break; From c787fa8e646957139d8086a098ebf1e36dffcc8d Mon Sep 17 00:00:00 2001 From: TSR Berry <20988865+TSRBerry@users.noreply.github.com> Date: Fri, 14 Oct 2022 15:16:38 +0200 Subject: [PATCH 2/4] bindings: Update Arm64 consts --- bindings/dotnet/UnicornManaged/Const/Arm64.fs | 56 ++++++++++--------- bindings/go/unicorn/arm64_const.go | 56 ++++++++++--------- bindings/java/unicorn/Arm64Const.java | 56 ++++++++++--------- bindings/pascal/unicorn/Arm64Const.pas | 56 ++++++++++--------- bindings/python/unicorn/arm64_const.py | 56 ++++++++++--------- .../lib/unicorn_engine/arm64_const.rb | 56 ++++++++++--------- 6 files changed, 180 insertions(+), 156 deletions(-) diff --git a/bindings/dotnet/UnicornManaged/Const/Arm64.fs b/bindings/dotnet/UnicornManaged/Const/Arm64.fs index f323fcf9..7357a252 100644 --- a/bindings/dotnet/UnicornManaged/Const/Arm64.fs +++ b/bindings/dotnet/UnicornManaged/Const/Arm64.fs @@ -288,37 +288,41 @@ module Arm64 = let UC_ARM64_REG_TPIDR_EL1 = 264 let UC_ARM64_REG_PSTATE = 265 + // floating point control and status registers + let UC_ARM64_REG_FPCR = 266 + let UC_ARM64_REG_FPSR = 267 + // exception link registers, depreciated, use UC_ARM64_REG_CP_REG instead - let UC_ARM64_REG_ELR_EL0 = 266 - let UC_ARM64_REG_ELR_EL1 = 267 - let UC_ARM64_REG_ELR_EL2 = 268 - let UC_ARM64_REG_ELR_EL3 = 269 + let UC_ARM64_REG_ELR_EL0 = 268 + let UC_ARM64_REG_ELR_EL1 = 269 + let UC_ARM64_REG_ELR_EL2 = 270 + let UC_ARM64_REG_ELR_EL3 = 271 // stack pointers registers, depreciated, use UC_ARM64_REG_CP_REG instead - let UC_ARM64_REG_SP_EL0 = 270 - let UC_ARM64_REG_SP_EL1 = 271 - let UC_ARM64_REG_SP_EL2 = 272 - let UC_ARM64_REG_SP_EL3 = 273 + let UC_ARM64_REG_SP_EL0 = 272 + let UC_ARM64_REG_SP_EL1 = 273 + let UC_ARM64_REG_SP_EL2 = 274 + let UC_ARM64_REG_SP_EL3 = 275 // other CP15 registers, depreciated, use UC_ARM64_REG_CP_REG instead - let UC_ARM64_REG_TTBR0_EL1 = 274 - let UC_ARM64_REG_TTBR1_EL1 = 275 - let UC_ARM64_REG_ESR_EL0 = 276 - let UC_ARM64_REG_ESR_EL1 = 277 - let UC_ARM64_REG_ESR_EL2 = 278 - let UC_ARM64_REG_ESR_EL3 = 279 - let UC_ARM64_REG_FAR_EL0 = 280 - let UC_ARM64_REG_FAR_EL1 = 281 - let UC_ARM64_REG_FAR_EL2 = 282 - let UC_ARM64_REG_FAR_EL3 = 283 - let UC_ARM64_REG_PAR_EL1 = 284 - let UC_ARM64_REG_MAIR_EL1 = 285 - let UC_ARM64_REG_VBAR_EL0 = 286 - let UC_ARM64_REG_VBAR_EL1 = 287 - let UC_ARM64_REG_VBAR_EL2 = 288 - let UC_ARM64_REG_VBAR_EL3 = 289 - let UC_ARM64_REG_CP_REG = 290 - let UC_ARM64_REG_ENDING = 291 + let UC_ARM64_REG_TTBR0_EL1 = 276 + let UC_ARM64_REG_TTBR1_EL1 = 277 + let UC_ARM64_REG_ESR_EL0 = 278 + let UC_ARM64_REG_ESR_EL1 = 279 + let UC_ARM64_REG_ESR_EL2 = 280 + let UC_ARM64_REG_ESR_EL3 = 281 + let UC_ARM64_REG_FAR_EL0 = 282 + let UC_ARM64_REG_FAR_EL1 = 283 + let UC_ARM64_REG_FAR_EL2 = 284 + let UC_ARM64_REG_FAR_EL3 = 285 + let UC_ARM64_REG_PAR_EL1 = 286 + let UC_ARM64_REG_MAIR_EL1 = 287 + let UC_ARM64_REG_VBAR_EL0 = 288 + let UC_ARM64_REG_VBAR_EL1 = 289 + let UC_ARM64_REG_VBAR_EL2 = 290 + let UC_ARM64_REG_VBAR_EL3 = 291 + let UC_ARM64_REG_CP_REG = 292 + let UC_ARM64_REG_ENDING = 293 // alias registers let UC_ARM64_REG_IP0 = 215 diff --git a/bindings/go/unicorn/arm64_const.go b/bindings/go/unicorn/arm64_const.go index 2f324154..7d89bace 100644 --- a/bindings/go/unicorn/arm64_const.go +++ b/bindings/go/unicorn/arm64_const.go @@ -283,37 +283,41 @@ const ( ARM64_REG_TPIDR_EL1 = 264 ARM64_REG_PSTATE = 265 +// floating point control and status registers + ARM64_REG_FPCR = 266 + ARM64_REG_FPSR = 267 + // exception link registers, depreciated, use UC_ARM64_REG_CP_REG instead - ARM64_REG_ELR_EL0 = 266 - ARM64_REG_ELR_EL1 = 267 - ARM64_REG_ELR_EL2 = 268 - ARM64_REG_ELR_EL3 = 269 + ARM64_REG_ELR_EL0 = 268 + ARM64_REG_ELR_EL1 = 269 + ARM64_REG_ELR_EL2 = 270 + ARM64_REG_ELR_EL3 = 271 // stack pointers registers, depreciated, use UC_ARM64_REG_CP_REG instead - ARM64_REG_SP_EL0 = 270 - ARM64_REG_SP_EL1 = 271 - ARM64_REG_SP_EL2 = 272 - ARM64_REG_SP_EL3 = 273 + ARM64_REG_SP_EL0 = 272 + ARM64_REG_SP_EL1 = 273 + ARM64_REG_SP_EL2 = 274 + ARM64_REG_SP_EL3 = 275 // other CP15 registers, depreciated, use UC_ARM64_REG_CP_REG instead - ARM64_REG_TTBR0_EL1 = 274 - ARM64_REG_TTBR1_EL1 = 275 - ARM64_REG_ESR_EL0 = 276 - ARM64_REG_ESR_EL1 = 277 - ARM64_REG_ESR_EL2 = 278 - ARM64_REG_ESR_EL3 = 279 - ARM64_REG_FAR_EL0 = 280 - ARM64_REG_FAR_EL1 = 281 - ARM64_REG_FAR_EL2 = 282 - ARM64_REG_FAR_EL3 = 283 - ARM64_REG_PAR_EL1 = 284 - ARM64_REG_MAIR_EL1 = 285 - ARM64_REG_VBAR_EL0 = 286 - ARM64_REG_VBAR_EL1 = 287 - ARM64_REG_VBAR_EL2 = 288 - ARM64_REG_VBAR_EL3 = 289 - ARM64_REG_CP_REG = 290 - ARM64_REG_ENDING = 291 + ARM64_REG_TTBR0_EL1 = 276 + ARM64_REG_TTBR1_EL1 = 277 + ARM64_REG_ESR_EL0 = 278 + ARM64_REG_ESR_EL1 = 279 + ARM64_REG_ESR_EL2 = 280 + ARM64_REG_ESR_EL3 = 281 + ARM64_REG_FAR_EL0 = 282 + ARM64_REG_FAR_EL1 = 283 + ARM64_REG_FAR_EL2 = 284 + ARM64_REG_FAR_EL3 = 285 + ARM64_REG_PAR_EL1 = 286 + ARM64_REG_MAIR_EL1 = 287 + ARM64_REG_VBAR_EL0 = 288 + ARM64_REG_VBAR_EL1 = 289 + ARM64_REG_VBAR_EL2 = 290 + ARM64_REG_VBAR_EL3 = 291 + ARM64_REG_CP_REG = 292 + ARM64_REG_ENDING = 293 // alias registers ARM64_REG_IP0 = 215 diff --git a/bindings/java/unicorn/Arm64Const.java b/bindings/java/unicorn/Arm64Const.java index 77b9e49a..699320af 100644 --- a/bindings/java/unicorn/Arm64Const.java +++ b/bindings/java/unicorn/Arm64Const.java @@ -285,37 +285,41 @@ public interface Arm64Const { public static final int UC_ARM64_REG_TPIDR_EL1 = 264; public static final int UC_ARM64_REG_PSTATE = 265; +// floating point control and status registers + public static final int UC_ARM64_REG_FPCR = 266; + public static final int UC_ARM64_REG_FPSR = 267; + // exception link registers, depreciated, use UC_ARM64_REG_CP_REG instead - public static final int UC_ARM64_REG_ELR_EL0 = 266; - public static final int UC_ARM64_REG_ELR_EL1 = 267; - public static final int UC_ARM64_REG_ELR_EL2 = 268; - public static final int UC_ARM64_REG_ELR_EL3 = 269; + public static final int UC_ARM64_REG_ELR_EL0 = 268; + public static final int UC_ARM64_REG_ELR_EL1 = 269; + public static final int UC_ARM64_REG_ELR_EL2 = 270; + public static final int UC_ARM64_REG_ELR_EL3 = 271; // stack pointers registers, depreciated, use UC_ARM64_REG_CP_REG instead - public static final int UC_ARM64_REG_SP_EL0 = 270; - public static final int UC_ARM64_REG_SP_EL1 = 271; - public static final int UC_ARM64_REG_SP_EL2 = 272; - public static final int UC_ARM64_REG_SP_EL3 = 273; + public static final int UC_ARM64_REG_SP_EL0 = 272; + public static final int UC_ARM64_REG_SP_EL1 = 273; + public static final int UC_ARM64_REG_SP_EL2 = 274; + public static final int UC_ARM64_REG_SP_EL3 = 275; // other CP15 registers, depreciated, use UC_ARM64_REG_CP_REG instead - public static final int UC_ARM64_REG_TTBR0_EL1 = 274; - public static final int UC_ARM64_REG_TTBR1_EL1 = 275; - public static final int UC_ARM64_REG_ESR_EL0 = 276; - public static final int UC_ARM64_REG_ESR_EL1 = 277; - public static final int UC_ARM64_REG_ESR_EL2 = 278; - public static final int UC_ARM64_REG_ESR_EL3 = 279; - public static final int UC_ARM64_REG_FAR_EL0 = 280; - public static final int UC_ARM64_REG_FAR_EL1 = 281; - public static final int UC_ARM64_REG_FAR_EL2 = 282; - public static final int UC_ARM64_REG_FAR_EL3 = 283; - public static final int UC_ARM64_REG_PAR_EL1 = 284; - public static final int UC_ARM64_REG_MAIR_EL1 = 285; - public static final int UC_ARM64_REG_VBAR_EL0 = 286; - public static final int UC_ARM64_REG_VBAR_EL1 = 287; - public static final int UC_ARM64_REG_VBAR_EL2 = 288; - public static final int UC_ARM64_REG_VBAR_EL3 = 289; - public static final int UC_ARM64_REG_CP_REG = 290; - public static final int UC_ARM64_REG_ENDING = 291; + public static final int UC_ARM64_REG_TTBR0_EL1 = 276; + public static final int UC_ARM64_REG_TTBR1_EL1 = 277; + public static final int UC_ARM64_REG_ESR_EL0 = 278; + public static final int UC_ARM64_REG_ESR_EL1 = 279; + public static final int UC_ARM64_REG_ESR_EL2 = 280; + public static final int UC_ARM64_REG_ESR_EL3 = 281; + public static final int UC_ARM64_REG_FAR_EL0 = 282; + public static final int UC_ARM64_REG_FAR_EL1 = 283; + public static final int UC_ARM64_REG_FAR_EL2 = 284; + public static final int UC_ARM64_REG_FAR_EL3 = 285; + public static final int UC_ARM64_REG_PAR_EL1 = 286; + public static final int UC_ARM64_REG_MAIR_EL1 = 287; + public static final int UC_ARM64_REG_VBAR_EL0 = 288; + public static final int UC_ARM64_REG_VBAR_EL1 = 289; + public static final int UC_ARM64_REG_VBAR_EL2 = 290; + public static final int UC_ARM64_REG_VBAR_EL3 = 291; + public static final int UC_ARM64_REG_CP_REG = 292; + public static final int UC_ARM64_REG_ENDING = 293; // alias registers public static final int UC_ARM64_REG_IP0 = 215; diff --git a/bindings/pascal/unicorn/Arm64Const.pas b/bindings/pascal/unicorn/Arm64Const.pas index 9e3939d3..05347e71 100644 --- a/bindings/pascal/unicorn/Arm64Const.pas +++ b/bindings/pascal/unicorn/Arm64Const.pas @@ -286,37 +286,41 @@ const UC_ARM64_REG_TPIDR_EL1 = 264; UC_ARM64_REG_PSTATE = 265; +// floating point control and status registers + UC_ARM64_REG_FPCR = 266; + UC_ARM64_REG_FPSR = 267; + // exception link registers, depreciated, use UC_ARM64_REG_CP_REG instead - UC_ARM64_REG_ELR_EL0 = 266; - UC_ARM64_REG_ELR_EL1 = 267; - UC_ARM64_REG_ELR_EL2 = 268; - UC_ARM64_REG_ELR_EL3 = 269; + UC_ARM64_REG_ELR_EL0 = 268; + UC_ARM64_REG_ELR_EL1 = 269; + UC_ARM64_REG_ELR_EL2 = 270; + UC_ARM64_REG_ELR_EL3 = 271; // stack pointers registers, depreciated, use UC_ARM64_REG_CP_REG instead - UC_ARM64_REG_SP_EL0 = 270; - UC_ARM64_REG_SP_EL1 = 271; - UC_ARM64_REG_SP_EL2 = 272; - UC_ARM64_REG_SP_EL3 = 273; + UC_ARM64_REG_SP_EL0 = 272; + UC_ARM64_REG_SP_EL1 = 273; + UC_ARM64_REG_SP_EL2 = 274; + UC_ARM64_REG_SP_EL3 = 275; // other CP15 registers, depreciated, use UC_ARM64_REG_CP_REG instead - UC_ARM64_REG_TTBR0_EL1 = 274; - UC_ARM64_REG_TTBR1_EL1 = 275; - UC_ARM64_REG_ESR_EL0 = 276; - UC_ARM64_REG_ESR_EL1 = 277; - UC_ARM64_REG_ESR_EL2 = 278; - UC_ARM64_REG_ESR_EL3 = 279; - UC_ARM64_REG_FAR_EL0 = 280; - UC_ARM64_REG_FAR_EL1 = 281; - UC_ARM64_REG_FAR_EL2 = 282; - UC_ARM64_REG_FAR_EL3 = 283; - UC_ARM64_REG_PAR_EL1 = 284; - UC_ARM64_REG_MAIR_EL1 = 285; - UC_ARM64_REG_VBAR_EL0 = 286; - UC_ARM64_REG_VBAR_EL1 = 287; - UC_ARM64_REG_VBAR_EL2 = 288; - UC_ARM64_REG_VBAR_EL3 = 289; - UC_ARM64_REG_CP_REG = 290; - UC_ARM64_REG_ENDING = 291; + UC_ARM64_REG_TTBR0_EL1 = 276; + UC_ARM64_REG_TTBR1_EL1 = 277; + UC_ARM64_REG_ESR_EL0 = 278; + UC_ARM64_REG_ESR_EL1 = 279; + UC_ARM64_REG_ESR_EL2 = 280; + UC_ARM64_REG_ESR_EL3 = 281; + UC_ARM64_REG_FAR_EL0 = 282; + UC_ARM64_REG_FAR_EL1 = 283; + UC_ARM64_REG_FAR_EL2 = 284; + UC_ARM64_REG_FAR_EL3 = 285; + UC_ARM64_REG_PAR_EL1 = 286; + UC_ARM64_REG_MAIR_EL1 = 287; + UC_ARM64_REG_VBAR_EL0 = 288; + UC_ARM64_REG_VBAR_EL1 = 289; + UC_ARM64_REG_VBAR_EL2 = 290; + UC_ARM64_REG_VBAR_EL3 = 291; + UC_ARM64_REG_CP_REG = 292; + UC_ARM64_REG_ENDING = 293; // alias registers UC_ARM64_REG_IP0 = 215; diff --git a/bindings/python/unicorn/arm64_const.py b/bindings/python/unicorn/arm64_const.py index 8d7c5a70..485daf43 100644 --- a/bindings/python/unicorn/arm64_const.py +++ b/bindings/python/unicorn/arm64_const.py @@ -281,37 +281,41 @@ UC_ARM64_REG_TPIDRRO_EL0 = 263 UC_ARM64_REG_TPIDR_EL1 = 264 UC_ARM64_REG_PSTATE = 265 +# floating point control and status registers +UC_ARM64_REG_FPCR = 266 +UC_ARM64_REG_FPSR = 267 + # exception link registers, depreciated, use UC_ARM64_REG_CP_REG instead -UC_ARM64_REG_ELR_EL0 = 266 -UC_ARM64_REG_ELR_EL1 = 267 -UC_ARM64_REG_ELR_EL2 = 268 -UC_ARM64_REG_ELR_EL3 = 269 +UC_ARM64_REG_ELR_EL0 = 268 +UC_ARM64_REG_ELR_EL1 = 269 +UC_ARM64_REG_ELR_EL2 = 270 +UC_ARM64_REG_ELR_EL3 = 271 # stack pointers registers, depreciated, use UC_ARM64_REG_CP_REG instead -UC_ARM64_REG_SP_EL0 = 270 -UC_ARM64_REG_SP_EL1 = 271 -UC_ARM64_REG_SP_EL2 = 272 -UC_ARM64_REG_SP_EL3 = 273 +UC_ARM64_REG_SP_EL0 = 272 +UC_ARM64_REG_SP_EL1 = 273 +UC_ARM64_REG_SP_EL2 = 274 +UC_ARM64_REG_SP_EL3 = 275 # other CP15 registers, depreciated, use UC_ARM64_REG_CP_REG instead -UC_ARM64_REG_TTBR0_EL1 = 274 -UC_ARM64_REG_TTBR1_EL1 = 275 -UC_ARM64_REG_ESR_EL0 = 276 -UC_ARM64_REG_ESR_EL1 = 277 -UC_ARM64_REG_ESR_EL2 = 278 -UC_ARM64_REG_ESR_EL3 = 279 -UC_ARM64_REG_FAR_EL0 = 280 -UC_ARM64_REG_FAR_EL1 = 281 -UC_ARM64_REG_FAR_EL2 = 282 -UC_ARM64_REG_FAR_EL3 = 283 -UC_ARM64_REG_PAR_EL1 = 284 -UC_ARM64_REG_MAIR_EL1 = 285 -UC_ARM64_REG_VBAR_EL0 = 286 -UC_ARM64_REG_VBAR_EL1 = 287 -UC_ARM64_REG_VBAR_EL2 = 288 -UC_ARM64_REG_VBAR_EL3 = 289 -UC_ARM64_REG_CP_REG = 290 -UC_ARM64_REG_ENDING = 291 +UC_ARM64_REG_TTBR0_EL1 = 276 +UC_ARM64_REG_TTBR1_EL1 = 277 +UC_ARM64_REG_ESR_EL0 = 278 +UC_ARM64_REG_ESR_EL1 = 279 +UC_ARM64_REG_ESR_EL2 = 280 +UC_ARM64_REG_ESR_EL3 = 281 +UC_ARM64_REG_FAR_EL0 = 282 +UC_ARM64_REG_FAR_EL1 = 283 +UC_ARM64_REG_FAR_EL2 = 284 +UC_ARM64_REG_FAR_EL3 = 285 +UC_ARM64_REG_PAR_EL1 = 286 +UC_ARM64_REG_MAIR_EL1 = 287 +UC_ARM64_REG_VBAR_EL0 = 288 +UC_ARM64_REG_VBAR_EL1 = 289 +UC_ARM64_REG_VBAR_EL2 = 290 +UC_ARM64_REG_VBAR_EL3 = 291 +UC_ARM64_REG_CP_REG = 292 +UC_ARM64_REG_ENDING = 293 # alias registers UC_ARM64_REG_IP0 = 215 diff --git a/bindings/ruby/unicorn_gem/lib/unicorn_engine/arm64_const.rb b/bindings/ruby/unicorn_gem/lib/unicorn_engine/arm64_const.rb index 6ec37708..3e379a43 100644 --- a/bindings/ruby/unicorn_gem/lib/unicorn_engine/arm64_const.rb +++ b/bindings/ruby/unicorn_gem/lib/unicorn_engine/arm64_const.rb @@ -283,37 +283,41 @@ module UnicornEngine UC_ARM64_REG_TPIDR_EL1 = 264 UC_ARM64_REG_PSTATE = 265 +# floating point control and status registers + UC_ARM64_REG_FPCR = 266 + UC_ARM64_REG_FPSR = 267 + # exception link registers, depreciated, use UC_ARM64_REG_CP_REG instead - UC_ARM64_REG_ELR_EL0 = 266 - UC_ARM64_REG_ELR_EL1 = 267 - UC_ARM64_REG_ELR_EL2 = 268 - UC_ARM64_REG_ELR_EL3 = 269 + UC_ARM64_REG_ELR_EL0 = 268 + UC_ARM64_REG_ELR_EL1 = 269 + UC_ARM64_REG_ELR_EL2 = 270 + UC_ARM64_REG_ELR_EL3 = 271 # stack pointers registers, depreciated, use UC_ARM64_REG_CP_REG instead - UC_ARM64_REG_SP_EL0 = 270 - UC_ARM64_REG_SP_EL1 = 271 - UC_ARM64_REG_SP_EL2 = 272 - UC_ARM64_REG_SP_EL3 = 273 + UC_ARM64_REG_SP_EL0 = 272 + UC_ARM64_REG_SP_EL1 = 273 + UC_ARM64_REG_SP_EL2 = 274 + UC_ARM64_REG_SP_EL3 = 275 # other CP15 registers, depreciated, use UC_ARM64_REG_CP_REG instead - UC_ARM64_REG_TTBR0_EL1 = 274 - UC_ARM64_REG_TTBR1_EL1 = 275 - UC_ARM64_REG_ESR_EL0 = 276 - UC_ARM64_REG_ESR_EL1 = 277 - UC_ARM64_REG_ESR_EL2 = 278 - UC_ARM64_REG_ESR_EL3 = 279 - UC_ARM64_REG_FAR_EL0 = 280 - UC_ARM64_REG_FAR_EL1 = 281 - UC_ARM64_REG_FAR_EL2 = 282 - UC_ARM64_REG_FAR_EL3 = 283 - UC_ARM64_REG_PAR_EL1 = 284 - UC_ARM64_REG_MAIR_EL1 = 285 - UC_ARM64_REG_VBAR_EL0 = 286 - UC_ARM64_REG_VBAR_EL1 = 287 - UC_ARM64_REG_VBAR_EL2 = 288 - UC_ARM64_REG_VBAR_EL3 = 289 - UC_ARM64_REG_CP_REG = 290 - UC_ARM64_REG_ENDING = 291 + UC_ARM64_REG_TTBR0_EL1 = 276 + UC_ARM64_REG_TTBR1_EL1 = 277 + UC_ARM64_REG_ESR_EL0 = 278 + UC_ARM64_REG_ESR_EL1 = 279 + UC_ARM64_REG_ESR_EL2 = 280 + UC_ARM64_REG_ESR_EL3 = 281 + UC_ARM64_REG_FAR_EL0 = 282 + UC_ARM64_REG_FAR_EL1 = 283 + UC_ARM64_REG_FAR_EL2 = 284 + UC_ARM64_REG_FAR_EL3 = 285 + UC_ARM64_REG_PAR_EL1 = 286 + UC_ARM64_REG_MAIR_EL1 = 287 + UC_ARM64_REG_VBAR_EL0 = 288 + UC_ARM64_REG_VBAR_EL1 = 289 + UC_ARM64_REG_VBAR_EL2 = 290 + UC_ARM64_REG_VBAR_EL3 = 291 + UC_ARM64_REG_CP_REG = 292 + UC_ARM64_REG_ENDING = 293 # alias registers UC_ARM64_REG_IP0 = 215 From 442dd437e10dbbcc522379da9adbbbf9dca9b2f2 Mon Sep 17 00:00:00 2001 From: TSR Berry <20988865+TSRBerry@users.noreply.github.com> Date: Fri, 14 Oct 2022 17:27:47 +0200 Subject: [PATCH 3/4] aarch64: Move FPCR and FPSR registers to not break compatibility Co-authored-by: merry --- include/unicorn/arm64.h | 8 ++++---- qemu/target/arm/unicorn_aarch64.c | 24 ++++++++++++------------ 2 files changed, 16 insertions(+), 16 deletions(-) diff --git a/include/unicorn/arm64.h b/include/unicorn/arm64.h index aab2ab9c..fd8192fb 100644 --- a/include/unicorn/arm64.h +++ b/include/unicorn/arm64.h @@ -313,10 +313,6 @@ typedef enum uc_arm64_reg { UC_ARM64_REG_PSTATE, - //> floating point control and status registers - UC_ARM64_REG_FPCR, - UC_ARM64_REG_FPSR, - //> exception link registers, depreciated, use UC_ARM64_REG_CP_REG instead UC_ARM64_REG_ELR_EL0, UC_ARM64_REG_ELR_EL1, @@ -354,6 +350,10 @@ typedef enum uc_arm64_reg { UC_ARM64_REG_CP_REG, + //> floating point control and status registers + UC_ARM64_REG_FPCR, + UC_ARM64_REG_FPSR, + UC_ARM64_REG_ENDING, // <-- mark the end of the list of registers //> alias registers diff --git a/qemu/target/arm/unicorn_aarch64.c b/qemu/target/arm/unicorn_aarch64.c index 4b533047..fec0db68 100644 --- a/qemu/target/arm/unicorn_aarch64.c +++ b/qemu/target/arm/unicorn_aarch64.c @@ -210,12 +210,6 @@ static uc_err reg_read(CPUARMState *env, unsigned int regid, void *value) case UC_ARM64_REG_PSTATE: *(uint32_t *)value = pstate_read(env); break; - case UC_ARM64_REG_FPCR: - *(uint32_t *)value = vfp_get_fpcr(env); - break; - case UC_ARM64_REG_FPSR: - *(uint32_t *)value = vfp_get_fpsr(env); - break; case UC_ARM64_REG_TTBR0_EL1: *(uint64_t *)value = env->cp15.ttbr0_el[1]; break; @@ -231,6 +225,12 @@ static uc_err reg_read(CPUARMState *env, unsigned int regid, void *value) case UC_ARM64_REG_CP_REG: ret = read_cp_reg(env, (uc_arm64_cp_reg *)value); break; + case UC_ARM64_REG_FPCR: + *(uint32_t *)value = vfp_get_fpcr(env); + break; + case UC_ARM64_REG_FPSR: + *(uint32_t *)value = vfp_get_fpsr(env); + break; } } @@ -309,12 +309,6 @@ static uc_err reg_write(CPUARMState *env, unsigned int regid, const void *value) case UC_ARM64_REG_PSTATE: pstate_write(env, *(uint32_t *)value); break; - case UC_ARM64_REG_FPCR: - vfp_set_fpcr(env, *(uint32_t *)value); - break; - case UC_ARM64_REG_FPSR: - vfp_set_fpsr(env, *(uint32_t *)value); - break; case UC_ARM64_REG_TTBR0_EL1: env->cp15.ttbr0_el[1] = *(uint64_t *)value; break; @@ -330,6 +324,12 @@ static uc_err reg_write(CPUARMState *env, unsigned int regid, const void *value) case UC_ARM64_REG_CP_REG: ret = write_cp_reg(env, (uc_arm64_cp_reg *)value); break; + case UC_ARM64_REG_FPCR: + vfp_set_fpcr(env, *(uint32_t *)value); + break; + case UC_ARM64_REG_FPSR: + vfp_set_fpsr(env, *(uint32_t *)value); + break; } } From 7b8b75b9f84ed2a7191130ebe965b8f6cd1872a0 Mon Sep 17 00:00:00 2001 From: TSR Berry <20988865+TSRBerry@users.noreply.github.com> Date: Fri, 14 Oct 2022 17:33:07 +0200 Subject: [PATCH 4/4] bindings: Adjust consts --- bindings/dotnet/UnicornManaged/Const/Arm64.fs | 58 +++++++++---------- bindings/go/unicorn/arm64_const.go | 58 +++++++++---------- bindings/java/unicorn/Arm64Const.java | 58 +++++++++---------- bindings/pascal/unicorn/Arm64Const.pas | 58 +++++++++---------- bindings/python/unicorn/arm64_const.py | 58 +++++++++---------- .../lib/unicorn_engine/arm64_const.rb | 58 +++++++++---------- 6 files changed, 174 insertions(+), 174 deletions(-) diff --git a/bindings/dotnet/UnicornManaged/Const/Arm64.fs b/bindings/dotnet/UnicornManaged/Const/Arm64.fs index 7357a252..4c509d03 100644 --- a/bindings/dotnet/UnicornManaged/Const/Arm64.fs +++ b/bindings/dotnet/UnicornManaged/Const/Arm64.fs @@ -288,40 +288,40 @@ module Arm64 = let UC_ARM64_REG_TPIDR_EL1 = 264 let UC_ARM64_REG_PSTATE = 265 - // floating point control and status registers - let UC_ARM64_REG_FPCR = 266 - let UC_ARM64_REG_FPSR = 267 - // exception link registers, depreciated, use UC_ARM64_REG_CP_REG instead - let UC_ARM64_REG_ELR_EL0 = 268 - let UC_ARM64_REG_ELR_EL1 = 269 - let UC_ARM64_REG_ELR_EL2 = 270 - let UC_ARM64_REG_ELR_EL3 = 271 + let UC_ARM64_REG_ELR_EL0 = 266 + let UC_ARM64_REG_ELR_EL1 = 267 + let UC_ARM64_REG_ELR_EL2 = 268 + let UC_ARM64_REG_ELR_EL3 = 269 // stack pointers registers, depreciated, use UC_ARM64_REG_CP_REG instead - let UC_ARM64_REG_SP_EL0 = 272 - let UC_ARM64_REG_SP_EL1 = 273 - let UC_ARM64_REG_SP_EL2 = 274 - let UC_ARM64_REG_SP_EL3 = 275 + let UC_ARM64_REG_SP_EL0 = 270 + let UC_ARM64_REG_SP_EL1 = 271 + let UC_ARM64_REG_SP_EL2 = 272 + let UC_ARM64_REG_SP_EL3 = 273 // other CP15 registers, depreciated, use UC_ARM64_REG_CP_REG instead - let UC_ARM64_REG_TTBR0_EL1 = 276 - let UC_ARM64_REG_TTBR1_EL1 = 277 - let UC_ARM64_REG_ESR_EL0 = 278 - let UC_ARM64_REG_ESR_EL1 = 279 - let UC_ARM64_REG_ESR_EL2 = 280 - let UC_ARM64_REG_ESR_EL3 = 281 - let UC_ARM64_REG_FAR_EL0 = 282 - let UC_ARM64_REG_FAR_EL1 = 283 - let UC_ARM64_REG_FAR_EL2 = 284 - let UC_ARM64_REG_FAR_EL3 = 285 - let UC_ARM64_REG_PAR_EL1 = 286 - let UC_ARM64_REG_MAIR_EL1 = 287 - let UC_ARM64_REG_VBAR_EL0 = 288 - let UC_ARM64_REG_VBAR_EL1 = 289 - let UC_ARM64_REG_VBAR_EL2 = 290 - let UC_ARM64_REG_VBAR_EL3 = 291 - let UC_ARM64_REG_CP_REG = 292 + let UC_ARM64_REG_TTBR0_EL1 = 274 + let UC_ARM64_REG_TTBR1_EL1 = 275 + let UC_ARM64_REG_ESR_EL0 = 276 + let UC_ARM64_REG_ESR_EL1 = 277 + let UC_ARM64_REG_ESR_EL2 = 278 + let UC_ARM64_REG_ESR_EL3 = 279 + let UC_ARM64_REG_FAR_EL0 = 280 + let UC_ARM64_REG_FAR_EL1 = 281 + let UC_ARM64_REG_FAR_EL2 = 282 + let UC_ARM64_REG_FAR_EL3 = 283 + let UC_ARM64_REG_PAR_EL1 = 284 + let UC_ARM64_REG_MAIR_EL1 = 285 + let UC_ARM64_REG_VBAR_EL0 = 286 + let UC_ARM64_REG_VBAR_EL1 = 287 + let UC_ARM64_REG_VBAR_EL2 = 288 + let UC_ARM64_REG_VBAR_EL3 = 289 + let UC_ARM64_REG_CP_REG = 290 + + // floating point control and status registers + let UC_ARM64_REG_FPCR = 291 + let UC_ARM64_REG_FPSR = 292 let UC_ARM64_REG_ENDING = 293 // alias registers diff --git a/bindings/go/unicorn/arm64_const.go b/bindings/go/unicorn/arm64_const.go index 7d89bace..e3548c78 100644 --- a/bindings/go/unicorn/arm64_const.go +++ b/bindings/go/unicorn/arm64_const.go @@ -283,40 +283,40 @@ const ( ARM64_REG_TPIDR_EL1 = 264 ARM64_REG_PSTATE = 265 -// floating point control and status registers - ARM64_REG_FPCR = 266 - ARM64_REG_FPSR = 267 - // exception link registers, depreciated, use UC_ARM64_REG_CP_REG instead - ARM64_REG_ELR_EL0 = 268 - ARM64_REG_ELR_EL1 = 269 - ARM64_REG_ELR_EL2 = 270 - ARM64_REG_ELR_EL3 = 271 + ARM64_REG_ELR_EL0 = 266 + ARM64_REG_ELR_EL1 = 267 + ARM64_REG_ELR_EL2 = 268 + ARM64_REG_ELR_EL3 = 269 // stack pointers registers, depreciated, use UC_ARM64_REG_CP_REG instead - ARM64_REG_SP_EL0 = 272 - ARM64_REG_SP_EL1 = 273 - ARM64_REG_SP_EL2 = 274 - ARM64_REG_SP_EL3 = 275 + ARM64_REG_SP_EL0 = 270 + ARM64_REG_SP_EL1 = 271 + ARM64_REG_SP_EL2 = 272 + ARM64_REG_SP_EL3 = 273 // other CP15 registers, depreciated, use UC_ARM64_REG_CP_REG instead - ARM64_REG_TTBR0_EL1 = 276 - ARM64_REG_TTBR1_EL1 = 277 - ARM64_REG_ESR_EL0 = 278 - ARM64_REG_ESR_EL1 = 279 - ARM64_REG_ESR_EL2 = 280 - ARM64_REG_ESR_EL3 = 281 - ARM64_REG_FAR_EL0 = 282 - ARM64_REG_FAR_EL1 = 283 - ARM64_REG_FAR_EL2 = 284 - ARM64_REG_FAR_EL3 = 285 - ARM64_REG_PAR_EL1 = 286 - ARM64_REG_MAIR_EL1 = 287 - ARM64_REG_VBAR_EL0 = 288 - ARM64_REG_VBAR_EL1 = 289 - ARM64_REG_VBAR_EL2 = 290 - ARM64_REG_VBAR_EL3 = 291 - ARM64_REG_CP_REG = 292 + ARM64_REG_TTBR0_EL1 = 274 + ARM64_REG_TTBR1_EL1 = 275 + ARM64_REG_ESR_EL0 = 276 + ARM64_REG_ESR_EL1 = 277 + ARM64_REG_ESR_EL2 = 278 + ARM64_REG_ESR_EL3 = 279 + ARM64_REG_FAR_EL0 = 280 + ARM64_REG_FAR_EL1 = 281 + ARM64_REG_FAR_EL2 = 282 + ARM64_REG_FAR_EL3 = 283 + ARM64_REG_PAR_EL1 = 284 + ARM64_REG_MAIR_EL1 = 285 + ARM64_REG_VBAR_EL0 = 286 + ARM64_REG_VBAR_EL1 = 287 + ARM64_REG_VBAR_EL2 = 288 + ARM64_REG_VBAR_EL3 = 289 + ARM64_REG_CP_REG = 290 + +// floating point control and status registers + ARM64_REG_FPCR = 291 + ARM64_REG_FPSR = 292 ARM64_REG_ENDING = 293 // alias registers diff --git a/bindings/java/unicorn/Arm64Const.java b/bindings/java/unicorn/Arm64Const.java index 699320af..bb196037 100644 --- a/bindings/java/unicorn/Arm64Const.java +++ b/bindings/java/unicorn/Arm64Const.java @@ -285,40 +285,40 @@ public interface Arm64Const { public static final int UC_ARM64_REG_TPIDR_EL1 = 264; public static final int UC_ARM64_REG_PSTATE = 265; -// floating point control and status registers - public static final int UC_ARM64_REG_FPCR = 266; - public static final int UC_ARM64_REG_FPSR = 267; - // exception link registers, depreciated, use UC_ARM64_REG_CP_REG instead - public static final int UC_ARM64_REG_ELR_EL0 = 268; - public static final int UC_ARM64_REG_ELR_EL1 = 269; - public static final int UC_ARM64_REG_ELR_EL2 = 270; - public static final int UC_ARM64_REG_ELR_EL3 = 271; + public static final int UC_ARM64_REG_ELR_EL0 = 266; + public static final int UC_ARM64_REG_ELR_EL1 = 267; + public static final int UC_ARM64_REG_ELR_EL2 = 268; + public static final int UC_ARM64_REG_ELR_EL3 = 269; // stack pointers registers, depreciated, use UC_ARM64_REG_CP_REG instead - public static final int UC_ARM64_REG_SP_EL0 = 272; - public static final int UC_ARM64_REG_SP_EL1 = 273; - public static final int UC_ARM64_REG_SP_EL2 = 274; - public static final int UC_ARM64_REG_SP_EL3 = 275; + public static final int UC_ARM64_REG_SP_EL0 = 270; + public static final int UC_ARM64_REG_SP_EL1 = 271; + public static final int UC_ARM64_REG_SP_EL2 = 272; + public static final int UC_ARM64_REG_SP_EL3 = 273; // other CP15 registers, depreciated, use UC_ARM64_REG_CP_REG instead - public static final int UC_ARM64_REG_TTBR0_EL1 = 276; - public static final int UC_ARM64_REG_TTBR1_EL1 = 277; - public static final int UC_ARM64_REG_ESR_EL0 = 278; - public static final int UC_ARM64_REG_ESR_EL1 = 279; - public static final int UC_ARM64_REG_ESR_EL2 = 280; - public static final int UC_ARM64_REG_ESR_EL3 = 281; - public static final int UC_ARM64_REG_FAR_EL0 = 282; - public static final int UC_ARM64_REG_FAR_EL1 = 283; - public static final int UC_ARM64_REG_FAR_EL2 = 284; - public static final int UC_ARM64_REG_FAR_EL3 = 285; - public static final int UC_ARM64_REG_PAR_EL1 = 286; - public static final int UC_ARM64_REG_MAIR_EL1 = 287; - public static final int UC_ARM64_REG_VBAR_EL0 = 288; - public static final int UC_ARM64_REG_VBAR_EL1 = 289; - public static final int UC_ARM64_REG_VBAR_EL2 = 290; - public static final int UC_ARM64_REG_VBAR_EL3 = 291; - public static final int UC_ARM64_REG_CP_REG = 292; + public static final int UC_ARM64_REG_TTBR0_EL1 = 274; + public static final int UC_ARM64_REG_TTBR1_EL1 = 275; + public static final int UC_ARM64_REG_ESR_EL0 = 276; + public static final int UC_ARM64_REG_ESR_EL1 = 277; + public static final int UC_ARM64_REG_ESR_EL2 = 278; + public static final int UC_ARM64_REG_ESR_EL3 = 279; + public static final int UC_ARM64_REG_FAR_EL0 = 280; + public static final int UC_ARM64_REG_FAR_EL1 = 281; + public static final int UC_ARM64_REG_FAR_EL2 = 282; + public static final int UC_ARM64_REG_FAR_EL3 = 283; + public static final int UC_ARM64_REG_PAR_EL1 = 284; + public static final int UC_ARM64_REG_MAIR_EL1 = 285; + public static final int UC_ARM64_REG_VBAR_EL0 = 286; + public static final int UC_ARM64_REG_VBAR_EL1 = 287; + public static final int UC_ARM64_REG_VBAR_EL2 = 288; + public static final int UC_ARM64_REG_VBAR_EL3 = 289; + public static final int UC_ARM64_REG_CP_REG = 290; + +// floating point control and status registers + public static final int UC_ARM64_REG_FPCR = 291; + public static final int UC_ARM64_REG_FPSR = 292; public static final int UC_ARM64_REG_ENDING = 293; // alias registers diff --git a/bindings/pascal/unicorn/Arm64Const.pas b/bindings/pascal/unicorn/Arm64Const.pas index 05347e71..800846b3 100644 --- a/bindings/pascal/unicorn/Arm64Const.pas +++ b/bindings/pascal/unicorn/Arm64Const.pas @@ -286,40 +286,40 @@ const UC_ARM64_REG_TPIDR_EL1 = 264; UC_ARM64_REG_PSTATE = 265; -// floating point control and status registers - UC_ARM64_REG_FPCR = 266; - UC_ARM64_REG_FPSR = 267; - // exception link registers, depreciated, use UC_ARM64_REG_CP_REG instead - UC_ARM64_REG_ELR_EL0 = 268; - UC_ARM64_REG_ELR_EL1 = 269; - UC_ARM64_REG_ELR_EL2 = 270; - UC_ARM64_REG_ELR_EL3 = 271; + UC_ARM64_REG_ELR_EL0 = 266; + UC_ARM64_REG_ELR_EL1 = 267; + UC_ARM64_REG_ELR_EL2 = 268; + UC_ARM64_REG_ELR_EL3 = 269; // stack pointers registers, depreciated, use UC_ARM64_REG_CP_REG instead - UC_ARM64_REG_SP_EL0 = 272; - UC_ARM64_REG_SP_EL1 = 273; - UC_ARM64_REG_SP_EL2 = 274; - UC_ARM64_REG_SP_EL3 = 275; + UC_ARM64_REG_SP_EL0 = 270; + UC_ARM64_REG_SP_EL1 = 271; + UC_ARM64_REG_SP_EL2 = 272; + UC_ARM64_REG_SP_EL3 = 273; // other CP15 registers, depreciated, use UC_ARM64_REG_CP_REG instead - UC_ARM64_REG_TTBR0_EL1 = 276; - UC_ARM64_REG_TTBR1_EL1 = 277; - UC_ARM64_REG_ESR_EL0 = 278; - UC_ARM64_REG_ESR_EL1 = 279; - UC_ARM64_REG_ESR_EL2 = 280; - UC_ARM64_REG_ESR_EL3 = 281; - UC_ARM64_REG_FAR_EL0 = 282; - UC_ARM64_REG_FAR_EL1 = 283; - UC_ARM64_REG_FAR_EL2 = 284; - UC_ARM64_REG_FAR_EL3 = 285; - UC_ARM64_REG_PAR_EL1 = 286; - UC_ARM64_REG_MAIR_EL1 = 287; - UC_ARM64_REG_VBAR_EL0 = 288; - UC_ARM64_REG_VBAR_EL1 = 289; - UC_ARM64_REG_VBAR_EL2 = 290; - UC_ARM64_REG_VBAR_EL3 = 291; - UC_ARM64_REG_CP_REG = 292; + UC_ARM64_REG_TTBR0_EL1 = 274; + UC_ARM64_REG_TTBR1_EL1 = 275; + UC_ARM64_REG_ESR_EL0 = 276; + UC_ARM64_REG_ESR_EL1 = 277; + UC_ARM64_REG_ESR_EL2 = 278; + UC_ARM64_REG_ESR_EL3 = 279; + UC_ARM64_REG_FAR_EL0 = 280; + UC_ARM64_REG_FAR_EL1 = 281; + UC_ARM64_REG_FAR_EL2 = 282; + UC_ARM64_REG_FAR_EL3 = 283; + UC_ARM64_REG_PAR_EL1 = 284; + UC_ARM64_REG_MAIR_EL1 = 285; + UC_ARM64_REG_VBAR_EL0 = 286; + UC_ARM64_REG_VBAR_EL1 = 287; + UC_ARM64_REG_VBAR_EL2 = 288; + UC_ARM64_REG_VBAR_EL3 = 289; + UC_ARM64_REG_CP_REG = 290; + +// floating point control and status registers + UC_ARM64_REG_FPCR = 291; + UC_ARM64_REG_FPSR = 292; UC_ARM64_REG_ENDING = 293; // alias registers diff --git a/bindings/python/unicorn/arm64_const.py b/bindings/python/unicorn/arm64_const.py index 485daf43..53135ab8 100644 --- a/bindings/python/unicorn/arm64_const.py +++ b/bindings/python/unicorn/arm64_const.py @@ -281,40 +281,40 @@ UC_ARM64_REG_TPIDRRO_EL0 = 263 UC_ARM64_REG_TPIDR_EL1 = 264 UC_ARM64_REG_PSTATE = 265 -# floating point control and status registers -UC_ARM64_REG_FPCR = 266 -UC_ARM64_REG_FPSR = 267 - # exception link registers, depreciated, use UC_ARM64_REG_CP_REG instead -UC_ARM64_REG_ELR_EL0 = 268 -UC_ARM64_REG_ELR_EL1 = 269 -UC_ARM64_REG_ELR_EL2 = 270 -UC_ARM64_REG_ELR_EL3 = 271 +UC_ARM64_REG_ELR_EL0 = 266 +UC_ARM64_REG_ELR_EL1 = 267 +UC_ARM64_REG_ELR_EL2 = 268 +UC_ARM64_REG_ELR_EL3 = 269 # stack pointers registers, depreciated, use UC_ARM64_REG_CP_REG instead -UC_ARM64_REG_SP_EL0 = 272 -UC_ARM64_REG_SP_EL1 = 273 -UC_ARM64_REG_SP_EL2 = 274 -UC_ARM64_REG_SP_EL3 = 275 +UC_ARM64_REG_SP_EL0 = 270 +UC_ARM64_REG_SP_EL1 = 271 +UC_ARM64_REG_SP_EL2 = 272 +UC_ARM64_REG_SP_EL3 = 273 # other CP15 registers, depreciated, use UC_ARM64_REG_CP_REG instead -UC_ARM64_REG_TTBR0_EL1 = 276 -UC_ARM64_REG_TTBR1_EL1 = 277 -UC_ARM64_REG_ESR_EL0 = 278 -UC_ARM64_REG_ESR_EL1 = 279 -UC_ARM64_REG_ESR_EL2 = 280 -UC_ARM64_REG_ESR_EL3 = 281 -UC_ARM64_REG_FAR_EL0 = 282 -UC_ARM64_REG_FAR_EL1 = 283 -UC_ARM64_REG_FAR_EL2 = 284 -UC_ARM64_REG_FAR_EL3 = 285 -UC_ARM64_REG_PAR_EL1 = 286 -UC_ARM64_REG_MAIR_EL1 = 287 -UC_ARM64_REG_VBAR_EL0 = 288 -UC_ARM64_REG_VBAR_EL1 = 289 -UC_ARM64_REG_VBAR_EL2 = 290 -UC_ARM64_REG_VBAR_EL3 = 291 -UC_ARM64_REG_CP_REG = 292 +UC_ARM64_REG_TTBR0_EL1 = 274 +UC_ARM64_REG_TTBR1_EL1 = 275 +UC_ARM64_REG_ESR_EL0 = 276 +UC_ARM64_REG_ESR_EL1 = 277 +UC_ARM64_REG_ESR_EL2 = 278 +UC_ARM64_REG_ESR_EL3 = 279 +UC_ARM64_REG_FAR_EL0 = 280 +UC_ARM64_REG_FAR_EL1 = 281 +UC_ARM64_REG_FAR_EL2 = 282 +UC_ARM64_REG_FAR_EL3 = 283 +UC_ARM64_REG_PAR_EL1 = 284 +UC_ARM64_REG_MAIR_EL1 = 285 +UC_ARM64_REG_VBAR_EL0 = 286 +UC_ARM64_REG_VBAR_EL1 = 287 +UC_ARM64_REG_VBAR_EL2 = 288 +UC_ARM64_REG_VBAR_EL3 = 289 +UC_ARM64_REG_CP_REG = 290 + +# floating point control and status registers +UC_ARM64_REG_FPCR = 291 +UC_ARM64_REG_FPSR = 292 UC_ARM64_REG_ENDING = 293 # alias registers diff --git a/bindings/ruby/unicorn_gem/lib/unicorn_engine/arm64_const.rb b/bindings/ruby/unicorn_gem/lib/unicorn_engine/arm64_const.rb index 3e379a43..aef319be 100644 --- a/bindings/ruby/unicorn_gem/lib/unicorn_engine/arm64_const.rb +++ b/bindings/ruby/unicorn_gem/lib/unicorn_engine/arm64_const.rb @@ -283,40 +283,40 @@ module UnicornEngine UC_ARM64_REG_TPIDR_EL1 = 264 UC_ARM64_REG_PSTATE = 265 -# floating point control and status registers - UC_ARM64_REG_FPCR = 266 - UC_ARM64_REG_FPSR = 267 - # exception link registers, depreciated, use UC_ARM64_REG_CP_REG instead - UC_ARM64_REG_ELR_EL0 = 268 - UC_ARM64_REG_ELR_EL1 = 269 - UC_ARM64_REG_ELR_EL2 = 270 - UC_ARM64_REG_ELR_EL3 = 271 + UC_ARM64_REG_ELR_EL0 = 266 + UC_ARM64_REG_ELR_EL1 = 267 + UC_ARM64_REG_ELR_EL2 = 268 + UC_ARM64_REG_ELR_EL3 = 269 # stack pointers registers, depreciated, use UC_ARM64_REG_CP_REG instead - UC_ARM64_REG_SP_EL0 = 272 - UC_ARM64_REG_SP_EL1 = 273 - UC_ARM64_REG_SP_EL2 = 274 - UC_ARM64_REG_SP_EL3 = 275 + UC_ARM64_REG_SP_EL0 = 270 + UC_ARM64_REG_SP_EL1 = 271 + UC_ARM64_REG_SP_EL2 = 272 + UC_ARM64_REG_SP_EL3 = 273 # other CP15 registers, depreciated, use UC_ARM64_REG_CP_REG instead - UC_ARM64_REG_TTBR0_EL1 = 276 - UC_ARM64_REG_TTBR1_EL1 = 277 - UC_ARM64_REG_ESR_EL0 = 278 - UC_ARM64_REG_ESR_EL1 = 279 - UC_ARM64_REG_ESR_EL2 = 280 - UC_ARM64_REG_ESR_EL3 = 281 - UC_ARM64_REG_FAR_EL0 = 282 - UC_ARM64_REG_FAR_EL1 = 283 - UC_ARM64_REG_FAR_EL2 = 284 - UC_ARM64_REG_FAR_EL3 = 285 - UC_ARM64_REG_PAR_EL1 = 286 - UC_ARM64_REG_MAIR_EL1 = 287 - UC_ARM64_REG_VBAR_EL0 = 288 - UC_ARM64_REG_VBAR_EL1 = 289 - UC_ARM64_REG_VBAR_EL2 = 290 - UC_ARM64_REG_VBAR_EL3 = 291 - UC_ARM64_REG_CP_REG = 292 + UC_ARM64_REG_TTBR0_EL1 = 274 + UC_ARM64_REG_TTBR1_EL1 = 275 + UC_ARM64_REG_ESR_EL0 = 276 + UC_ARM64_REG_ESR_EL1 = 277 + UC_ARM64_REG_ESR_EL2 = 278 + UC_ARM64_REG_ESR_EL3 = 279 + UC_ARM64_REG_FAR_EL0 = 280 + UC_ARM64_REG_FAR_EL1 = 281 + UC_ARM64_REG_FAR_EL2 = 282 + UC_ARM64_REG_FAR_EL3 = 283 + UC_ARM64_REG_PAR_EL1 = 284 + UC_ARM64_REG_MAIR_EL1 = 285 + UC_ARM64_REG_VBAR_EL0 = 286 + UC_ARM64_REG_VBAR_EL1 = 287 + UC_ARM64_REG_VBAR_EL2 = 288 + UC_ARM64_REG_VBAR_EL3 = 289 + UC_ARM64_REG_CP_REG = 290 + +# floating point control and status registers + UC_ARM64_REG_FPCR = 291 + UC_ARM64_REG_FPSR = 292 UC_ARM64_REG_ENDING = 293 # alias registers