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Format unicorn_arm and unicorn_aarch64

This commit is contained in:
lazymio 2021-11-01 10:17:58 +01:00
parent 0a3e46bf4f
commit 6c3960242b
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GPG Key ID: DFF27E34A47CB873
3 changed files with 377 additions and 346 deletions
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2
format.sh
View File

@ -5,4 +5,4 @@ find ./msvc -maxdepth 1 "(" -name "*.c" -or -name "*.h" ")" -exec clang-format -
find ./include -maxdepth 2 "(" -name "*.c" -or -name "*.h" ")" -exec clang-format -i -style=file "{}" ";"
find ./tests/unit -maxdepth 1 "(" -name "*.c" -or -name "*.h" ")" -exec clang-format -i -style=file "{}" ";"
find ./samples -maxdepth 1 "(" -name "*.c" -or -name "*.h" ")" -exec clang-format -i -style=file "{}" ";"
find ./qemu "(" -name "unicorn.c" -or -name "unicorn.h" ")" -exec clang-format -i -style=file "{}" ";"
find ./qemu "(" -name "unicorn.c" -or -name "unicorn.h" -or -name "unicorn_arm.c" -or -name "unicorn_aarch64.c" ")" -exec clang-format -i -style=file "{}" ";"

54
qemu/target/arm/unicorn_aarch64.c
View File

@ -38,11 +38,13 @@ static void arm64_release(void* ctx)
g_free(fast->table);
}
QLIST_FOREACH_SAFE(entry, &cpu->pre_el_change_hooks, node, next) {
QLIST_FOREACH_SAFE(entry, &cpu->pre_el_change_hooks, node, next)
{
QLIST_SAFE_REMOVE(entry, node);
g_free(entry);
}
QLIST_FOREACH_SAFE(entry, &cpu->el_change_hooks, node, next) {
QLIST_FOREACH_SAFE(entry, &cpu->el_change_hooks, node, next)
{
QLIST_SAFE_REMOVE(entry, node);
g_free(entry);
}
@ -105,11 +107,14 @@ static void reg_read(CPUARMState *env, unsigned int regid, void *value)
} else if (regid >= UC_ARM64_REG_D0 && regid <= UC_ARM64_REG_D31) {
*(float64 *)value = env->vfp.zregs[regid - UC_ARM64_REG_D0].d[0];
} else if (regid >= UC_ARM64_REG_S0 && regid <= UC_ARM64_REG_S31) {
*(int32_t*)value = READ_DWORD(env->vfp.zregs[regid - UC_ARM64_REG_S0].d[0]);
*(int32_t *)value =
READ_DWORD(env->vfp.zregs[regid - UC_ARM64_REG_S0].d[0]);
} else if (regid >= UC_ARM64_REG_H0 && regid <= UC_ARM64_REG_H31) {
*(int16_t*)value = READ_WORD(env->vfp.zregs[regid - UC_ARM64_REG_H0].d[0]);
*(int16_t *)value =
READ_WORD(env->vfp.zregs[regid - UC_ARM64_REG_H0].d[0]);
} else if (regid >= UC_ARM64_REG_B0 && regid <= UC_ARM64_REG_B31) {
*(int8_t*)value = READ_BYTE_L(env->vfp.zregs[regid - UC_ARM64_REG_B0].d[0]);
*(int8_t *)value =
READ_BYTE_L(env->vfp.zregs[regid - UC_ARM64_REG_B0].d[0]);
} else if (regid >= UC_ARM64_REG_ELR_EL0 && regid <= UC_ARM64_REG_ELR_EL3) {
*(uint64_t *)value = env->elr_el[regid - UC_ARM64_REG_ELR_EL0];
} else if (regid >= UC_ARM64_REG_SP_EL0 && regid <= UC_ARM64_REG_SP_EL3) {
@ -118,11 +123,13 @@ static void reg_read(CPUARMState *env, unsigned int regid, void *value)
*(uint64_t *)value = env->cp15.esr_el[regid - UC_ARM64_REG_ESR_EL0];
} else if (regid >= UC_ARM64_REG_FAR_EL0 && regid <= UC_ARM64_REG_FAR_EL3) {
*(uint64_t *)value = env->cp15.far_el[regid - UC_ARM64_REG_FAR_EL0];
} else if (regid >= UC_ARM64_REG_VBAR_EL0 && regid <= UC_ARM64_REG_VBAR_EL3) {
} else if (regid >= UC_ARM64_REG_VBAR_EL0 &&
regid <= UC_ARM64_REG_VBAR_EL3) {
*(uint64_t *)value = env->cp15.vbar_el[regid - UC_ARM64_REG_VBAR_EL0];
} else {
switch (regid) {
default: break;
default:
break;
case UC_ARM64_REG_CPACR_EL1:
// *(uint32_t *)value = env->cp15.c1_coproc;
break;
@ -188,11 +195,14 @@ static void reg_write(CPUARMState *env, unsigned int regid, const void *value)
} else if (regid >= UC_ARM64_REG_D0 && regid <= UC_ARM64_REG_D31) {
env->vfp.zregs[regid - UC_ARM64_REG_D0].d[0] = *(float64 *)value;
} else if (regid >= UC_ARM64_REG_S0 && regid <= UC_ARM64_REG_S31) {
WRITE_DWORD(env->vfp.zregs[regid - UC_ARM64_REG_S0].d[0], *(int32_t*) value);
WRITE_DWORD(env->vfp.zregs[regid - UC_ARM64_REG_S0].d[0],
*(int32_t *)value);
} else if (regid >= UC_ARM64_REG_H0 && regid <= UC_ARM64_REG_H31) {
WRITE_WORD(env->vfp.zregs[regid - UC_ARM64_REG_H0].d[0], *(int16_t*) value);
WRITE_WORD(env->vfp.zregs[regid - UC_ARM64_REG_H0].d[0],
*(int16_t *)value);
} else if (regid >= UC_ARM64_REG_B0 && regid <= UC_ARM64_REG_B31) {
WRITE_BYTE_L(env->vfp.zregs[regid - UC_ARM64_REG_B0].d[0], *(int8_t*) value);
WRITE_BYTE_L(env->vfp.zregs[regid - UC_ARM64_REG_B0].d[0],
*(int8_t *)value);
} else if (regid >= UC_ARM64_REG_ELR_EL0 && regid <= UC_ARM64_REG_ELR_EL3) {
env->elr_el[regid - UC_ARM64_REG_ELR_EL0] = *(uint64_t *)value;
} else if (regid >= UC_ARM64_REG_SP_EL0 && regid <= UC_ARM64_REG_SP_EL3) {
@ -201,11 +211,13 @@ static void reg_write(CPUARMState *env, unsigned int regid, const void *value)
env->cp15.esr_el[regid - UC_ARM64_REG_ESR_EL0] = *(uint64_t *)value;
} else if (regid >= UC_ARM64_REG_FAR_EL0 && regid <= UC_ARM64_REG_FAR_EL3) {
env->cp15.far_el[regid - UC_ARM64_REG_FAR_EL0] = *(uint64_t *)value;
} else if (regid >= UC_ARM64_REG_VBAR_EL0 && regid <= UC_ARM64_REG_VBAR_EL3) {
} else if (regid >= UC_ARM64_REG_VBAR_EL0 &&
regid <= UC_ARM64_REG_VBAR_EL3) {
env->cp15.vbar_el[regid - UC_ARM64_REG_VBAR_EL0] = *(uint64_t *)value;
} else {
switch (regid) {
default: break;
default:
break;
case UC_ARM64_REG_CPACR_EL1:
// env->cp15.c1_coproc = *(uint32_t *)value;
break;
@ -254,7 +266,8 @@ static void reg_write(CPUARMState *env, unsigned int regid, const void *value)
return;
}
int arm64_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int count)
int arm64_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals,
int count)
{
CPUARMState *env = &(ARM_CPU(uc->cpu)->env);
int i;
@ -268,7 +281,8 @@ int arm64_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int co
return 0;
}
int arm64_reg_write(struct uc_struct *uc, unsigned int *regs, void* const* vals, int count)
int arm64_reg_write(struct uc_struct *uc, unsigned int *regs, void *const *vals,
int count)
{
CPUARMState *env = &(ARM_CPU(uc->cpu)->env);
int i;
@ -289,9 +303,11 @@ int arm64_reg_write(struct uc_struct *uc, unsigned int *regs, void* const* vals,
DEFAULT_VISIBILITY
#ifdef TARGET_WORDS_BIGENDIAN
int arm64eb_context_reg_read(struct uc_context *ctx, unsigned int *regs, void **vals, int count)
int arm64eb_context_reg_read(struct uc_context *ctx, unsigned int *regs,
void **vals, int count)
#else
int arm64_context_reg_read(struct uc_context *ctx, unsigned int *regs, void **vals, int count)
int arm64_context_reg_read(struct uc_context *ctx, unsigned int *regs,
void **vals, int count)
#endif
{
CPUARMState *env = (CPUARMState *)ctx->data;
@ -308,9 +324,11 @@ int arm64_context_reg_read(struct uc_context *ctx, unsigned int *regs, void **va
DEFAULT_VISIBILITY
#ifdef TARGET_WORDS_BIGENDIAN
int arm64eb_context_reg_write(struct uc_context *ctx, unsigned int *regs, void* const* vals, int count)
int arm64eb_context_reg_write(struct uc_context *ctx, unsigned int *regs,
void *const *vals, int count)
#else
int arm64_context_reg_write(struct uc_context *ctx, unsigned int *regs, void* const* vals, int count)
int arm64_context_reg_write(struct uc_context *ctx, unsigned int *regs,
void *const *vals, int count)
#endif
{
CPUARMState *env = (CPUARMState *)ctx->data;

39
qemu/target/arm/unicorn_arm.c
View File

@ -40,11 +40,13 @@ static void arm_release(void *ctx)
g_free(fast->table);
}
QLIST_FOREACH_SAFE(entry, &cpu->pre_el_change_hooks, node, next) {
QLIST_FOREACH_SAFE(entry, &cpu->pre_el_change_hooks, node, next)
{
QLIST_SAFE_REMOVE(entry, node);
g_free(entry);
}
QLIST_FOREACH_SAFE(entry, &cpu->el_change_hooks, node, next) {
QLIST_FOREACH_SAFE(entry, &cpu->el_change_hooks, node, next)
{
QLIST_SAFE_REMOVE(entry, node);
g_free(entry);
}
@ -120,7 +122,8 @@ static uint32_t v7m_mrs_xpsr(CPUARMState *env, uint32_t reg)
return xpsr_read(env) & mask;
}
static void v7m_msr_xpsr(CPUARMState *env, uint32_t mask, uint32_t reg, uint32_t val)
static void v7m_msr_xpsr(CPUARMState *env, uint32_t mask, uint32_t reg,
uint32_t val)
{
uint32_t xpsrmask = 0;
@ -157,7 +160,8 @@ static void reg_read(CPUARMState *env, unsigned int regid, void *value)
if (arm_feature(env, ARM_FEATURE_M)) {
*(int32_t *)value = v7m_mrs_xpsr(env, 0);
} else {
*(int32_t *)value = cpsr_read(env) & (CPSR_NZCV | CPSR_Q | CPSR_GE);
*(int32_t *)value =
cpsr_read(env) & (CPSR_NZCV | CPSR_Q | CPSR_GE);
}
break;
case UC_ARM_REG_APSR_NZCV:
@ -246,7 +250,8 @@ static void reg_write(CPUARMState *env, unsigned int regid, const void *value)
switch (regid) {
case UC_ARM_REG_APSR:
if (!arm_feature(env, ARM_FEATURE_M)) {
cpsr_write(env, *(uint32_t *)value, (CPSR_NZCV | CPSR_Q | CPSR_GE), CPSRWriteRaw);
cpsr_write(env, *(uint32_t *)value,
(CPSR_NZCV | CPSR_Q | CPSR_GE), CPSRWriteRaw);
} else {
// Same with UC_ARM_REG_APSR_NZCVQ
v7m_msr_xpsr(env, 0b1000, 0, *(uint32_t *)value);
@ -361,7 +366,8 @@ static void reg_write(CPUARMState *env, unsigned int regid, const void *value)
return;
}
int arm_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int count)
int arm_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals,
int count)
{
CPUARMState *env = &(ARM_CPU(uc->cpu)->env);
int i;
@ -375,7 +381,8 @@ int arm_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int coun
return 0;
}
int arm_reg_write(struct uc_struct *uc, unsigned int *regs, void* const* vals, int count)
int arm_reg_write(struct uc_struct *uc, unsigned int *regs, void *const *vals,
int count)
{
CPUArchState *env = &(ARM_CPU(uc->cpu)->env);
int i;
@ -396,9 +403,11 @@ int arm_reg_write(struct uc_struct *uc, unsigned int *regs, void* const* vals, i
DEFAULT_VISIBILITY
#ifdef TARGET_WORDS_BIGENDIAN
int armeb_context_reg_read(struct uc_context *ctx, unsigned int *regs, void **vals, int count)
int armeb_context_reg_read(struct uc_context *ctx, unsigned int *regs,
void **vals, int count)
#else
int arm_context_reg_read(struct uc_context *ctx, unsigned int *regs, void **vals, int count)
int arm_context_reg_read(struct uc_context *ctx, unsigned int *regs,
void **vals, int count)
#endif
{
CPUARMState *env = (CPUARMState *)ctx->data;
@ -415,9 +424,11 @@ int arm_context_reg_read(struct uc_context *ctx, unsigned int *regs, void **vals
DEFAULT_VISIBILITY
#ifdef TARGET_WORDS_BIGENDIAN
int armeb_context_reg_write(struct uc_context *ctx, unsigned int *regs, void* const* vals, int count)
int armeb_context_reg_write(struct uc_context *ctx, unsigned int *regs,
void *const *vals, int count)
#else
int arm_context_reg_write(struct uc_context *ctx, unsigned int *regs, void* const* vals, int count)
int arm_context_reg_write(struct uc_context *ctx, unsigned int *regs,
void *const *vals, int count)
#endif
{
CPUARMState *env = (CPUARMState *)ctx->data;
@ -446,7 +457,8 @@ static bool arm_stop_interrupt(struct uc_struct *uc, int intno)
}
}
static uc_err arm_query(struct uc_struct *uc, uc_query_type type, size_t *result)
static uc_err arm_query(struct uc_struct *uc, uc_query_type type,
size_t *result)
{
CPUState *mycpu = uc->cpu;
uint32_t mode;
@ -456,7 +468,8 @@ static uc_err arm_query(struct uc_struct *uc, uc_query_type type, size_t *result
// zero out ARM/THUMB mode
mode = uc->mode & ~(UC_MODE_ARM | UC_MODE_THUMB);
// THUMB mode or ARM MOde
mode += ((ARM_CPU(mycpu)->env.thumb != 0)? UC_MODE_THUMB : UC_MODE_ARM);
mode +=
((ARM_CPU(mycpu)->env.thumb != 0) ? UC_MODE_THUMB : UC_MODE_ARM);
*result = mode;
return UC_ERR_OK;
default: