From 6c3960242b39239f1b5ae7acf50229cbc7e80c70 Mon Sep 17 00:00:00 2001 From: lazymio Date: Mon, 1 Nov 2021 10:17:58 +0100 Subject: [PATCH] Format unicorn_arm and unicorn_aarch64 --- format.sh | 2 +- qemu/target/arm/unicorn_aarch64.c | 270 +++++++++--------- qemu/target/arm/unicorn_arm.c | 451 +++++++++++++++--------------- 3 files changed, 377 insertions(+), 346 deletions(-) diff --git a/format.sh b/format.sh index d4418b15..0bf864e8 100644 --- a/format.sh +++ b/format.sh @@ -5,4 +5,4 @@ find ./msvc -maxdepth 1 "(" -name "*.c" -or -name "*.h" ")" -exec clang-format - find ./include -maxdepth 2 "(" -name "*.c" -or -name "*.h" ")" -exec clang-format -i -style=file "{}" ";" find ./tests/unit -maxdepth 1 "(" -name "*.c" -or -name "*.h" ")" -exec clang-format -i -style=file "{}" ";" find ./samples -maxdepth 1 "(" -name "*.c" -or -name "*.h" ")" -exec clang-format -i -style=file "{}" ";" -find ./qemu "(" -name "unicorn.c" -or -name "unicorn.h" ")" -exec clang-format -i -style=file "{}" ";" +find ./qemu "(" -name "unicorn.c" -or -name "unicorn.h" -or -name "unicorn_arm.c" -or -name "unicorn_aarch64.c" ")" -exec clang-format -i -style=file "{}" ";" diff --git a/qemu/target/arm/unicorn_aarch64.c b/qemu/target/arm/unicorn_aarch64.c index 14361f1c..872ed08a 100644 --- a/qemu/target/arm/unicorn_aarch64.c +++ b/qemu/target/arm/unicorn_aarch64.c @@ -17,7 +17,7 @@ static void arm64_set_pc(struct uc_struct *uc, uint64_t address) ((CPUARMState *)uc->cpu->env_ptr)->pc = address; } -static void arm64_release(void* ctx) +static void arm64_release(void *ctx) { int i; TCGContext *tcg_ctx = (TCGContext *)ctx; @@ -38,11 +38,13 @@ static void arm64_release(void* ctx) g_free(fast->table); } - QLIST_FOREACH_SAFE(entry, &cpu->pre_el_change_hooks, node, next) { + QLIST_FOREACH_SAFE(entry, &cpu->pre_el_change_hooks, node, next) + { QLIST_SAFE_REMOVE(entry, node); g_free(entry); } - QLIST_FOREACH_SAFE(entry, &cpu->el_change_hooks, node, next) { + QLIST_FOREACH_SAFE(entry, &cpu->el_change_hooks, node, next) + { QLIST_SAFE_REMOVE(entry, node); g_free(entry); } @@ -98,73 +100,78 @@ static void reg_read(CPUARMState *env, unsigned int regid, void *value) } else if (regid >= UC_ARM64_REG_W0 && regid <= UC_ARM64_REG_W30) { *(int32_t *)value = READ_DWORD(env->xregs[regid - UC_ARM64_REG_W0]); } else if (regid >= UC_ARM64_REG_Q0 && regid <= UC_ARM64_REG_Q31) { // FIXME - float64 *dst = (float64*) value; + float64 *dst = (float64 *)value; uint32_t reg_index = regid - UC_ARM64_REG_Q0; dst[0] = env->vfp.zregs[reg_index].d[0]; dst[1] = env->vfp.zregs[reg_index].d[1]; } else if (regid >= UC_ARM64_REG_D0 && regid <= UC_ARM64_REG_D31) { - *(float64*)value = env->vfp.zregs[regid - UC_ARM64_REG_D0].d[0]; + *(float64 *)value = env->vfp.zregs[regid - UC_ARM64_REG_D0].d[0]; } else if (regid >= UC_ARM64_REG_S0 && regid <= UC_ARM64_REG_S31) { - *(int32_t*)value = READ_DWORD(env->vfp.zregs[regid - UC_ARM64_REG_S0].d[0]); + *(int32_t *)value = + READ_DWORD(env->vfp.zregs[regid - UC_ARM64_REG_S0].d[0]); } else if (regid >= UC_ARM64_REG_H0 && regid <= UC_ARM64_REG_H31) { - *(int16_t*)value = READ_WORD(env->vfp.zregs[regid - UC_ARM64_REG_H0].d[0]); + *(int16_t *)value = + READ_WORD(env->vfp.zregs[regid - UC_ARM64_REG_H0].d[0]); } else if (regid >= UC_ARM64_REG_B0 && regid <= UC_ARM64_REG_B31) { - *(int8_t*)value = READ_BYTE_L(env->vfp.zregs[regid - UC_ARM64_REG_B0].d[0]); + *(int8_t *)value = + READ_BYTE_L(env->vfp.zregs[regid - UC_ARM64_REG_B0].d[0]); } else if (regid >= UC_ARM64_REG_ELR_EL0 && regid <= UC_ARM64_REG_ELR_EL3) { - *(uint64_t*)value = env->elr_el[regid - UC_ARM64_REG_ELR_EL0]; + *(uint64_t *)value = env->elr_el[regid - UC_ARM64_REG_ELR_EL0]; } else if (regid >= UC_ARM64_REG_SP_EL0 && regid <= UC_ARM64_REG_SP_EL3) { - *(uint64_t*)value = env->sp_el[regid - UC_ARM64_REG_SP_EL0]; + *(uint64_t *)value = env->sp_el[regid - UC_ARM64_REG_SP_EL0]; } else if (regid >= UC_ARM64_REG_ESR_EL0 && regid <= UC_ARM64_REG_ESR_EL3) { - *(uint64_t*)value = env->cp15.esr_el[regid - UC_ARM64_REG_ESR_EL0]; + *(uint64_t *)value = env->cp15.esr_el[regid - UC_ARM64_REG_ESR_EL0]; } else if (regid >= UC_ARM64_REG_FAR_EL0 && regid <= UC_ARM64_REG_FAR_EL3) { - *(uint64_t*)value = env->cp15.far_el[regid - UC_ARM64_REG_FAR_EL0]; - } else if (regid >= UC_ARM64_REG_VBAR_EL0 && regid <= UC_ARM64_REG_VBAR_EL3) { - *(uint64_t*)value = env->cp15.vbar_el[regid - UC_ARM64_REG_VBAR_EL0]; + *(uint64_t *)value = env->cp15.far_el[regid - UC_ARM64_REG_FAR_EL0]; + } else if (regid >= UC_ARM64_REG_VBAR_EL0 && + regid <= UC_ARM64_REG_VBAR_EL3) { + *(uint64_t *)value = env->cp15.vbar_el[regid - UC_ARM64_REG_VBAR_EL0]; } else { - switch(regid) { - default: break; - case UC_ARM64_REG_CPACR_EL1: - // *(uint32_t *)value = env->cp15.c1_coproc; - break; - case UC_ARM64_REG_TPIDR_EL0: - // *(int64_t *)value = env->cp15.tpidr_el0; - break; - case UC_ARM64_REG_TPIDRRO_EL0: - // *(int64_t *)value = env->cp15.tpidrro_el0; - break; - case UC_ARM64_REG_TPIDR_EL1: - // *(int64_t *)value = env->cp15.tpidr_el1; - break; - case UC_ARM64_REG_X29: - *(int64_t *)value = env->xregs[29]; - break; - case UC_ARM64_REG_X30: - *(int64_t *)value = env->xregs[30]; - break; - case UC_ARM64_REG_PC: - *(uint64_t *)value = env->pc; - break; - case UC_ARM64_REG_SP: - *(int64_t *)value = env->xregs[31]; - break; - case UC_ARM64_REG_NZCV: - *(int32_t *)value = cpsr_read(env) & CPSR_NZCV; - break; - case UC_ARM64_REG_PSTATE: - *(uint32_t *)value = pstate_read(env); - break; - case UC_ARM64_REG_TTBR0_EL1: - // *(uint64_t *)value = env->cp15.ttbr0_el1; - break; - case UC_ARM64_REG_TTBR1_EL1: - // *(uint64_t *)value = env->cp15.ttbr1_el1; - break; - case UC_ARM64_REG_PAR_EL1: - // *(uint64_t *)value = env->cp15.par_el1; - break; - case UC_ARM64_REG_MAIR_EL1: - // *(uint64_t *)value = env->cp15.mair_el1; - break; + switch (regid) { + default: + break; + case UC_ARM64_REG_CPACR_EL1: + // *(uint32_t *)value = env->cp15.c1_coproc; + break; + case UC_ARM64_REG_TPIDR_EL0: + // *(int64_t *)value = env->cp15.tpidr_el0; + break; + case UC_ARM64_REG_TPIDRRO_EL0: + // *(int64_t *)value = env->cp15.tpidrro_el0; + break; + case UC_ARM64_REG_TPIDR_EL1: + // *(int64_t *)value = env->cp15.tpidr_el1; + break; + case UC_ARM64_REG_X29: + *(int64_t *)value = env->xregs[29]; + break; + case UC_ARM64_REG_X30: + *(int64_t *)value = env->xregs[30]; + break; + case UC_ARM64_REG_PC: + *(uint64_t *)value = env->pc; + break; + case UC_ARM64_REG_SP: + *(int64_t *)value = env->xregs[31]; + break; + case UC_ARM64_REG_NZCV: + *(int32_t *)value = cpsr_read(env) & CPSR_NZCV; + break; + case UC_ARM64_REG_PSTATE: + *(uint32_t *)value = pstate_read(env); + break; + case UC_ARM64_REG_TTBR0_EL1: + // *(uint64_t *)value = env->cp15.ttbr0_el1; + break; + case UC_ARM64_REG_TTBR1_EL1: + // *(uint64_t *)value = env->cp15.ttbr1_el1; + break; + case UC_ARM64_REG_PAR_EL1: + // *(uint64_t *)value = env->cp15.par_el1; + break; + case UC_ARM64_REG_MAIR_EL1: + // *(uint64_t *)value = env->cp15.mair_el1; + break; } } @@ -181,82 +188,88 @@ static void reg_write(CPUARMState *env, unsigned int regid, const void *value) } else if (regid >= UC_ARM64_REG_W0 && regid <= UC_ARM64_REG_W30) { WRITE_DWORD(env->xregs[regid - UC_ARM64_REG_W0], *(uint32_t *)value); } else if (regid >= UC_ARM64_REG_Q0 && regid <= UC_ARM64_REG_Q31) { - float64 *src = (float64*) value; + float64 *src = (float64 *)value; uint32_t reg_index = regid - UC_ARM64_REG_Q0; env->vfp.zregs[reg_index].d[0] = src[0]; env->vfp.zregs[reg_index].d[1] = src[1]; } else if (regid >= UC_ARM64_REG_D0 && regid <= UC_ARM64_REG_D31) { - env->vfp.zregs[regid - UC_ARM64_REG_D0].d[0] = * (float64*) value; + env->vfp.zregs[regid - UC_ARM64_REG_D0].d[0] = *(float64 *)value; } else if (regid >= UC_ARM64_REG_S0 && regid <= UC_ARM64_REG_S31) { - WRITE_DWORD(env->vfp.zregs[regid - UC_ARM64_REG_S0].d[0], *(int32_t*) value); + WRITE_DWORD(env->vfp.zregs[regid - UC_ARM64_REG_S0].d[0], + *(int32_t *)value); } else if (regid >= UC_ARM64_REG_H0 && regid <= UC_ARM64_REG_H31) { - WRITE_WORD(env->vfp.zregs[regid - UC_ARM64_REG_H0].d[0], *(int16_t*) value); + WRITE_WORD(env->vfp.zregs[regid - UC_ARM64_REG_H0].d[0], + *(int16_t *)value); } else if (regid >= UC_ARM64_REG_B0 && regid <= UC_ARM64_REG_B31) { - WRITE_BYTE_L(env->vfp.zregs[regid - UC_ARM64_REG_B0].d[0], *(int8_t*) value); + WRITE_BYTE_L(env->vfp.zregs[regid - UC_ARM64_REG_B0].d[0], + *(int8_t *)value); } else if (regid >= UC_ARM64_REG_ELR_EL0 && regid <= UC_ARM64_REG_ELR_EL3) { - env->elr_el[regid - UC_ARM64_REG_ELR_EL0] = *(uint64_t*)value; + env->elr_el[regid - UC_ARM64_REG_ELR_EL0] = *(uint64_t *)value; } else if (regid >= UC_ARM64_REG_SP_EL0 && regid <= UC_ARM64_REG_SP_EL3) { - env->sp_el[regid - UC_ARM64_REG_SP_EL0] = *(uint64_t*)value; + env->sp_el[regid - UC_ARM64_REG_SP_EL0] = *(uint64_t *)value; } else if (regid >= UC_ARM64_REG_ESR_EL0 && regid <= UC_ARM64_REG_ESR_EL3) { - env->cp15.esr_el[regid - UC_ARM64_REG_ESR_EL0] = *(uint64_t*)value; + env->cp15.esr_el[regid - UC_ARM64_REG_ESR_EL0] = *(uint64_t *)value; } else if (regid >= UC_ARM64_REG_FAR_EL0 && regid <= UC_ARM64_REG_FAR_EL3) { - env->cp15.far_el[regid - UC_ARM64_REG_FAR_EL0] = *(uint64_t*)value; - } else if (regid >= UC_ARM64_REG_VBAR_EL0 && regid <= UC_ARM64_REG_VBAR_EL3) { - env->cp15.vbar_el[regid - UC_ARM64_REG_VBAR_EL0] = *(uint64_t*)value; + env->cp15.far_el[regid - UC_ARM64_REG_FAR_EL0] = *(uint64_t *)value; + } else if (regid >= UC_ARM64_REG_VBAR_EL0 && + regid <= UC_ARM64_REG_VBAR_EL3) { + env->cp15.vbar_el[regid - UC_ARM64_REG_VBAR_EL0] = *(uint64_t *)value; } else { - switch(regid) { - default: break; - case UC_ARM64_REG_CPACR_EL1: - //env->cp15.c1_coproc = *(uint32_t *)value; - break; - case UC_ARM64_REG_TPIDR_EL0: - //env->cp15.tpidr_el0 = *(uint64_t *)value; - break; - case UC_ARM64_REG_TPIDRRO_EL0: - //env->cp15.tpidrro_el0 = *(uint64_t *)value; - break; - case UC_ARM64_REG_TPIDR_EL1: - //env->cp15.tpidr_el1 = *(uint64_t *)value; - break; - case UC_ARM64_REG_X29: - env->xregs[29] = *(uint64_t *)value; - break; - case UC_ARM64_REG_X30: - env->xregs[30] = *(uint64_t *)value; - break; - case UC_ARM64_REG_PC: - env->pc = *(uint64_t *)value; - break; - case UC_ARM64_REG_SP: - env->xregs[31] = *(uint64_t *)value; - break; - case UC_ARM64_REG_NZCV: - //cpsr_write(env, *(uint32_t *)value, CPSR_NZCV); - break; - case UC_ARM64_REG_PSTATE: - pstate_write(env, *(uint32_t *)value); - break; - case UC_ARM64_REG_TTBR0_EL1: - //env->cp15.ttbr0_el1 = *(uint64_t *)value; - break; - case UC_ARM64_REG_TTBR1_EL1: - //env->cp15.ttbr1_el1 = *(uint64_t *)value; - break; - case UC_ARM64_REG_PAR_EL1: - //env->cp15.par_el1 = *(uint64_t *)value; - break; - case UC_ARM64_REG_MAIR_EL1: - //env->cp15.mair_el1 = *(uint64_t *)value; - break; + switch (regid) { + default: + break; + case UC_ARM64_REG_CPACR_EL1: + // env->cp15.c1_coproc = *(uint32_t *)value; + break; + case UC_ARM64_REG_TPIDR_EL0: + // env->cp15.tpidr_el0 = *(uint64_t *)value; + break; + case UC_ARM64_REG_TPIDRRO_EL0: + // env->cp15.tpidrro_el0 = *(uint64_t *)value; + break; + case UC_ARM64_REG_TPIDR_EL1: + // env->cp15.tpidr_el1 = *(uint64_t *)value; + break; + case UC_ARM64_REG_X29: + env->xregs[29] = *(uint64_t *)value; + break; + case UC_ARM64_REG_X30: + env->xregs[30] = *(uint64_t *)value; + break; + case UC_ARM64_REG_PC: + env->pc = *(uint64_t *)value; + break; + case UC_ARM64_REG_SP: + env->xregs[31] = *(uint64_t *)value; + break; + case UC_ARM64_REG_NZCV: + // cpsr_write(env, *(uint32_t *)value, CPSR_NZCV); + break; + case UC_ARM64_REG_PSTATE: + pstate_write(env, *(uint32_t *)value); + break; + case UC_ARM64_REG_TTBR0_EL1: + // env->cp15.ttbr0_el1 = *(uint64_t *)value; + break; + case UC_ARM64_REG_TTBR1_EL1: + // env->cp15.ttbr1_el1 = *(uint64_t *)value; + break; + case UC_ARM64_REG_PAR_EL1: + // env->cp15.par_el1 = *(uint64_t *)value; + break; + case UC_ARM64_REG_MAIR_EL1: + // env->cp15.mair_el1 = *(uint64_t *)value; + break; } } return; } -int arm64_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int count) +int arm64_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, + int count) { - CPUARMState *env= &(ARM_CPU(uc->cpu)->env); + CPUARMState *env = &(ARM_CPU(uc->cpu)->env); int i; for (i = 0; i < count; i++) { @@ -268,16 +281,17 @@ int arm64_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int co return 0; } -int arm64_reg_write(struct uc_struct *uc, unsigned int *regs, void* const* vals, int count) +int arm64_reg_write(struct uc_struct *uc, unsigned int *regs, void *const *vals, + int count) { - CPUARMState *env= &(ARM_CPU(uc->cpu)->env); + CPUARMState *env = &(ARM_CPU(uc->cpu)->env); int i; for (i = 0; i < count; i++) { unsigned int regid = regs[i]; const void *value = vals[i]; reg_write(env, regid, value); - if(regid == UC_ARM64_REG_PC){ + if (regid == UC_ARM64_REG_PC) { // force to quit execution and flush TB uc->quit_request = true; uc_emu_stop(uc); @@ -289,12 +303,14 @@ int arm64_reg_write(struct uc_struct *uc, unsigned int *regs, void* const* vals, DEFAULT_VISIBILITY #ifdef TARGET_WORDS_BIGENDIAN -int arm64eb_context_reg_read(struct uc_context *ctx, unsigned int *regs, void **vals, int count) +int arm64eb_context_reg_read(struct uc_context *ctx, unsigned int *regs, + void **vals, int count) #else -int arm64_context_reg_read(struct uc_context *ctx, unsigned int *regs, void **vals, int count) +int arm64_context_reg_read(struct uc_context *ctx, unsigned int *regs, + void **vals, int count) #endif { - CPUARMState *env= (CPUARMState *)ctx->data; + CPUARMState *env = (CPUARMState *)ctx->data; int i; for (i = 0; i < count; i++) { @@ -308,12 +324,14 @@ int arm64_context_reg_read(struct uc_context *ctx, unsigned int *regs, void **va DEFAULT_VISIBILITY #ifdef TARGET_WORDS_BIGENDIAN -int arm64eb_context_reg_write(struct uc_context *ctx, unsigned int *regs, void* const* vals, int count) +int arm64eb_context_reg_write(struct uc_context *ctx, unsigned int *regs, + void *const *vals, int count) #else -int arm64_context_reg_write(struct uc_context *ctx, unsigned int *regs, void* const* vals, int count) +int arm64_context_reg_write(struct uc_context *ctx, unsigned int *regs, + void *const *vals, int count) #endif { - CPUARMState *env= (CPUARMState *)ctx->data; + CPUARMState *env = (CPUARMState *)ctx->data; int i; for (i = 0; i < count; i++) { @@ -339,9 +357,9 @@ static int arm64_cpus_init(struct uc_struct *uc, const char *cpu_model) DEFAULT_VISIBILITY #ifdef TARGET_WORDS_BIGENDIAN -void arm64eb_uc_init(struct uc_struct* uc) +void arm64eb_uc_init(struct uc_struct *uc) #else -void arm64_uc_init(struct uc_struct* uc) +void arm64_uc_init(struct uc_struct *uc) #endif { uc->reg_read = arm64_reg_read; diff --git a/qemu/target/arm/unicorn_arm.c b/qemu/target/arm/unicorn_arm.c index 9a5a698d..2b30db80 100644 --- a/qemu/target/arm/unicorn_arm.c +++ b/qemu/target/arm/unicorn_arm.c @@ -23,7 +23,7 @@ static void arm_release(void *ctx) { int i; TCGContext *tcg_ctx = (TCGContext *)ctx; - ARMCPU* cpu = (ARMCPU *)tcg_ctx->uc->cpu; + ARMCPU *cpu = (ARMCPU *)tcg_ctx->uc->cpu; CPUTLBDesc *d = cpu->neg.tlb.d; CPUTLBDescFast *f = cpu->neg.tlb.f; CPUTLBDesc *desc; @@ -40,11 +40,13 @@ static void arm_release(void *ctx) g_free(fast->table); } - QLIST_FOREACH_SAFE(entry, &cpu->pre_el_change_hooks, node, next) { + QLIST_FOREACH_SAFE(entry, &cpu->pre_el_change_hooks, node, next) + { QLIST_SAFE_REMOVE(entry, node); g_free(entry); } - QLIST_FOREACH_SAFE(entry, &cpu->el_change_hooks, node, next) { + QLIST_FOREACH_SAFE(entry, &cpu->el_change_hooks, node, next) + { QLIST_SAFE_REMOVE(entry, node); g_free(entry); } @@ -120,7 +122,8 @@ static uint32_t v7m_mrs_xpsr(CPUARMState *env, uint32_t reg) return xpsr_read(env) & mask; } -static void v7m_msr_xpsr(CPUARMState *env, uint32_t mask, uint32_t reg, uint32_t val) +static void v7m_msr_xpsr(CPUARMState *env, uint32_t mask, uint32_t reg, + uint32_t val) { uint32_t xpsrmask = 0; @@ -150,85 +153,86 @@ static void reg_read(CPUARMState *env, unsigned int regid, void *value) *(int32_t *)value = env->regs[regid - UC_ARM_REG_R0]; } else if (regid >= UC_ARM_REG_D0 && regid <= UC_ARM_REG_D31) { uint32_t reg_index = regid - UC_ARM_REG_D0; - *(float64 *)value = env->vfp.zregs[reg_index / 2].d[reg_index & 1]; + *(float64 *)value = env->vfp.zregs[reg_index / 2].d[reg_index & 1]; } else { - switch(regid) { - case UC_ARM_REG_APSR: - if (arm_feature(env, ARM_FEATURE_M)) { - *(int32_t *)value = v7m_mrs_xpsr(env, 0); - } else { - *(int32_t *)value = cpsr_read(env) & (CPSR_NZCV | CPSR_Q | CPSR_GE); - } - break; - case UC_ARM_REG_APSR_NZCV: - *(int32_t *)value = cpsr_read(env) & CPSR_NZCV; - break; - case UC_ARM_REG_CPSR: - *(int32_t *)value = cpsr_read(env); - break; - case UC_ARM_REG_SPSR: - *(int32_t *)value = env->spsr; - break; - //case UC_ARM_REG_SP: - case UC_ARM_REG_R13: - *(int32_t *)value = env->regs[13]; - break; - //case UC_ARM_REG_LR: - case UC_ARM_REG_R14: - *(int32_t *)value = env->regs[14]; - break; - //case UC_ARM_REG_PC: - case UC_ARM_REG_R15: - *(int32_t *)value = env->regs[15]; - break; - case UC_ARM_REG_C1_C0_2: - *(int32_t *)value = env->cp15.cpacr_el1; - break; - case UC_ARM_REG_C13_C0_3: - *(int32_t *)value = env->cp15.tpidrro_el[0]; - break; - case UC_ARM_REG_FPEXC: - *(int32_t *)value = env->vfp.xregs[ARM_VFP_FPEXC]; - break; - case UC_ARM_REG_IPSR: - *(int32_t *)value = v7m_mrs_xpsr(env, 5); - break; - case UC_ARM_REG_MSP: - *(uint32_t *)value = helper_v7m_mrs(env, 8); - break; - case UC_ARM_REG_PSP: - *(uint32_t *)value = helper_v7m_mrs(env, 9); - break; - case UC_ARM_REG_IAPSR: - *(int32_t *)value = v7m_mrs_xpsr(env, 1); - break; - case UC_ARM_REG_EAPSR: - *(int32_t *)value = v7m_mrs_xpsr(env, 2); - break; - case UC_ARM_REG_XPSR: - *(int32_t *)value = v7m_mrs_xpsr(env, 3); - break; - case UC_ARM_REG_EPSR: - *(int32_t *)value = v7m_mrs_xpsr(env, 6); - break; - case UC_ARM_REG_IEPSR: - *(int32_t *)value = v7m_mrs_xpsr(env, 7); - break; - case UC_ARM_REG_PRIMASK: - *(uint32_t *)value = helper_v7m_mrs(env, 16); - break; - case UC_ARM_REG_BASEPRI: - *(uint32_t *)value = helper_v7m_mrs(env, 17); - break; - case UC_ARM_REG_BASEPRI_MAX: - *(uint32_t *)value = helper_v7m_mrs(env, 18); - break; - case UC_ARM_REG_FAULTMASK: - *(uint32_t *)value = helper_v7m_mrs(env, 19); - break; - case UC_ARM_REG_CONTROL: - *(uint32_t *)value = helper_v7m_mrs(env, 20); - break; + switch (regid) { + case UC_ARM_REG_APSR: + if (arm_feature(env, ARM_FEATURE_M)) { + *(int32_t *)value = v7m_mrs_xpsr(env, 0); + } else { + *(int32_t *)value = + cpsr_read(env) & (CPSR_NZCV | CPSR_Q | CPSR_GE); + } + break; + case UC_ARM_REG_APSR_NZCV: + *(int32_t *)value = cpsr_read(env) & CPSR_NZCV; + break; + case UC_ARM_REG_CPSR: + *(int32_t *)value = cpsr_read(env); + break; + case UC_ARM_REG_SPSR: + *(int32_t *)value = env->spsr; + break; + // case UC_ARM_REG_SP: + case UC_ARM_REG_R13: + *(int32_t *)value = env->regs[13]; + break; + // case UC_ARM_REG_LR: + case UC_ARM_REG_R14: + *(int32_t *)value = env->regs[14]; + break; + // case UC_ARM_REG_PC: + case UC_ARM_REG_R15: + *(int32_t *)value = env->regs[15]; + break; + case UC_ARM_REG_C1_C0_2: + *(int32_t *)value = env->cp15.cpacr_el1; + break; + case UC_ARM_REG_C13_C0_3: + *(int32_t *)value = env->cp15.tpidrro_el[0]; + break; + case UC_ARM_REG_FPEXC: + *(int32_t *)value = env->vfp.xregs[ARM_VFP_FPEXC]; + break; + case UC_ARM_REG_IPSR: + *(int32_t *)value = v7m_mrs_xpsr(env, 5); + break; + case UC_ARM_REG_MSP: + *(uint32_t *)value = helper_v7m_mrs(env, 8); + break; + case UC_ARM_REG_PSP: + *(uint32_t *)value = helper_v7m_mrs(env, 9); + break; + case UC_ARM_REG_IAPSR: + *(int32_t *)value = v7m_mrs_xpsr(env, 1); + break; + case UC_ARM_REG_EAPSR: + *(int32_t *)value = v7m_mrs_xpsr(env, 2); + break; + case UC_ARM_REG_XPSR: + *(int32_t *)value = v7m_mrs_xpsr(env, 3); + break; + case UC_ARM_REG_EPSR: + *(int32_t *)value = v7m_mrs_xpsr(env, 6); + break; + case UC_ARM_REG_IEPSR: + *(int32_t *)value = v7m_mrs_xpsr(env, 7); + break; + case UC_ARM_REG_PRIMASK: + *(uint32_t *)value = helper_v7m_mrs(env, 16); + break; + case UC_ARM_REG_BASEPRI: + *(uint32_t *)value = helper_v7m_mrs(env, 17); + break; + case UC_ARM_REG_BASEPRI_MAX: + *(uint32_t *)value = helper_v7m_mrs(env, 18); + break; + case UC_ARM_REG_FAULTMASK: + *(uint32_t *)value = helper_v7m_mrs(env, 19); + break; + case UC_ARM_REG_CONTROL: + *(uint32_t *)value = helper_v7m_mrs(env, 20); + break; } } @@ -243,125 +247,127 @@ static void reg_write(CPUARMState *env, unsigned int regid, const void *value) uint32_t reg_index = regid - UC_ARM_REG_D0; env->vfp.zregs[reg_index / 2].d[reg_index & 1] = *(float64 *)value; } else { - switch(regid) { - case UC_ARM_REG_APSR: - if (!arm_feature(env, ARM_FEATURE_M)) { - cpsr_write(env, *(uint32_t *)value, (CPSR_NZCV | CPSR_Q | CPSR_GE), CPSRWriteRaw); - } else { - // Same with UC_ARM_REG_APSR_NZCVQ - v7m_msr_xpsr(env, 0b1000, 0, *(uint32_t *)value); - } - break; - case UC_ARM_REG_APSR_NZCV: - cpsr_write(env, *(uint32_t *)value, CPSR_NZCV, CPSRWriteRaw); - break; - case UC_ARM_REG_CPSR: - cpsr_write(env, *(uint32_t *)value, ~0, CPSRWriteRaw); - break; - case UC_ARM_REG_SPSR: - env->spsr = *(uint32_t *)value; - break; - //case UC_ARM_REG_SP: - case UC_ARM_REG_R13: - env->regs[13] = *(uint32_t *)value; - break; - //case UC_ARM_REG_LR: - case UC_ARM_REG_R14: - env->regs[14] = *(uint32_t *)value; - break; - //case UC_ARM_REG_PC: - case UC_ARM_REG_R15: - env->pc = (*(uint32_t *)value & ~1); - env->thumb = (*(uint32_t *)value & 1); - env->uc->thumb = (*(uint32_t *)value & 1); - env->regs[15] = (*(uint32_t *)value & ~1); - break; + switch (regid) { + case UC_ARM_REG_APSR: + if (!arm_feature(env, ARM_FEATURE_M)) { + cpsr_write(env, *(uint32_t *)value, + (CPSR_NZCV | CPSR_Q | CPSR_GE), CPSRWriteRaw); + } else { + // Same with UC_ARM_REG_APSR_NZCVQ + v7m_msr_xpsr(env, 0b1000, 0, *(uint32_t *)value); + } + break; + case UC_ARM_REG_APSR_NZCV: + cpsr_write(env, *(uint32_t *)value, CPSR_NZCV, CPSRWriteRaw); + break; + case UC_ARM_REG_CPSR: + cpsr_write(env, *(uint32_t *)value, ~0, CPSRWriteRaw); + break; + case UC_ARM_REG_SPSR: + env->spsr = *(uint32_t *)value; + break; + // case UC_ARM_REG_SP: + case UC_ARM_REG_R13: + env->regs[13] = *(uint32_t *)value; + break; + // case UC_ARM_REG_LR: + case UC_ARM_REG_R14: + env->regs[14] = *(uint32_t *)value; + break; + // case UC_ARM_REG_PC: + case UC_ARM_REG_R15: + env->pc = (*(uint32_t *)value & ~1); + env->thumb = (*(uint32_t *)value & 1); + env->uc->thumb = (*(uint32_t *)value & 1); + env->regs[15] = (*(uint32_t *)value & ~1); + break; // case UC_ARM_REG_C1_C0_2: // env->cp15.c1_coproc = *(int32_t *)value; // break; - case UC_ARM_REG_C13_C0_3: - env->cp15.tpidrro_el[0] = *(int32_t *)value; - break; - case UC_ARM_REG_FPEXC: - env->vfp.xregs[ARM_VFP_FPEXC] = *(int32_t *)value; - break; - case UC_ARM_REG_IPSR: - v7m_msr_xpsr(env, 0b1000, 5, *(uint32_t *)value); - break; - case UC_ARM_REG_MSP: - helper_v7m_msr(env, 8, *(uint32_t *)value); - break; - case UC_ARM_REG_PSP: - helper_v7m_msr(env, 9, *(uint32_t *)value); - break; - case UC_ARM_REG_CONTROL: - helper_v7m_msr(env, 20, *(uint32_t *)value); - break; - case UC_ARM_REG_EPSR: - v7m_msr_xpsr(env, 0b1000, 6, *(uint32_t *)value); - break; - case UC_ARM_REG_IEPSR: - v7m_msr_xpsr(env, 0b1000, 7, *(uint32_t *)value); - break; - case UC_ARM_REG_PRIMASK: - helper_v7m_msr(env, 16, *(uint32_t *)value); - break; - case UC_ARM_REG_BASEPRI: - helper_v7m_msr(env, 17, *(uint32_t *)value); - break; - case UC_ARM_REG_BASEPRI_MAX: - helper_v7m_msr(env, 18, *(uint32_t *)value); - break; - case UC_ARM_REG_FAULTMASK: - helper_v7m_msr(env, 19, *(uint32_t *)value); - break; - case UC_ARM_REG_APSR_NZCVQ: - v7m_msr_xpsr(env, 0b1000, 0, *(uint32_t *)value); - break; - case UC_ARM_REG_APSR_G: - v7m_msr_xpsr(env, 0b0100, 0, *(uint32_t *)value); - break; - case UC_ARM_REG_APSR_NZCVQG: - v7m_msr_xpsr(env, 0b1100, 0, *(uint32_t *)value); - break; - case UC_ARM_REG_IAPSR: - case UC_ARM_REG_IAPSR_NZCVQ: - v7m_msr_xpsr(env, 0b1000, 1, *(uint32_t *)value); - break; - case UC_ARM_REG_IAPSR_G: - v7m_msr_xpsr(env, 0b0100, 1, *(uint32_t *)value); - break; - case UC_ARM_REG_IAPSR_NZCVQG: - v7m_msr_xpsr(env, 0b1100, 1, *(uint32_t *)value); - break; - case UC_ARM_REG_EAPSR: - case UC_ARM_REG_EAPSR_NZCVQ: - v7m_msr_xpsr(env, 0b1000, 2, *(uint32_t *)value); - break; - case UC_ARM_REG_EAPSR_G: - v7m_msr_xpsr(env, 0b0100, 2, *(uint32_t *)value); - break; - case UC_ARM_REG_EAPSR_NZCVQG: - v7m_msr_xpsr(env, 0b1100, 2, *(uint32_t *)value); - break; - case UC_ARM_REG_XPSR: - case UC_ARM_REG_XPSR_NZCVQ: - v7m_msr_xpsr(env, 0b1000, 3, *(uint32_t *)value); - break; - case UC_ARM_REG_XPSR_G: - v7m_msr_xpsr(env, 0b0100, 3, *(uint32_t *)value); - break; - case UC_ARM_REG_XPSR_NZCVQG: - v7m_msr_xpsr(env, 0b1100, 3, *(uint32_t *)value); - break; + case UC_ARM_REG_C13_C0_3: + env->cp15.tpidrro_el[0] = *(int32_t *)value; + break; + case UC_ARM_REG_FPEXC: + env->vfp.xregs[ARM_VFP_FPEXC] = *(int32_t *)value; + break; + case UC_ARM_REG_IPSR: + v7m_msr_xpsr(env, 0b1000, 5, *(uint32_t *)value); + break; + case UC_ARM_REG_MSP: + helper_v7m_msr(env, 8, *(uint32_t *)value); + break; + case UC_ARM_REG_PSP: + helper_v7m_msr(env, 9, *(uint32_t *)value); + break; + case UC_ARM_REG_CONTROL: + helper_v7m_msr(env, 20, *(uint32_t *)value); + break; + case UC_ARM_REG_EPSR: + v7m_msr_xpsr(env, 0b1000, 6, *(uint32_t *)value); + break; + case UC_ARM_REG_IEPSR: + v7m_msr_xpsr(env, 0b1000, 7, *(uint32_t *)value); + break; + case UC_ARM_REG_PRIMASK: + helper_v7m_msr(env, 16, *(uint32_t *)value); + break; + case UC_ARM_REG_BASEPRI: + helper_v7m_msr(env, 17, *(uint32_t *)value); + break; + case UC_ARM_REG_BASEPRI_MAX: + helper_v7m_msr(env, 18, *(uint32_t *)value); + break; + case UC_ARM_REG_FAULTMASK: + helper_v7m_msr(env, 19, *(uint32_t *)value); + break; + case UC_ARM_REG_APSR_NZCVQ: + v7m_msr_xpsr(env, 0b1000, 0, *(uint32_t *)value); + break; + case UC_ARM_REG_APSR_G: + v7m_msr_xpsr(env, 0b0100, 0, *(uint32_t *)value); + break; + case UC_ARM_REG_APSR_NZCVQG: + v7m_msr_xpsr(env, 0b1100, 0, *(uint32_t *)value); + break; + case UC_ARM_REG_IAPSR: + case UC_ARM_REG_IAPSR_NZCVQ: + v7m_msr_xpsr(env, 0b1000, 1, *(uint32_t *)value); + break; + case UC_ARM_REG_IAPSR_G: + v7m_msr_xpsr(env, 0b0100, 1, *(uint32_t *)value); + break; + case UC_ARM_REG_IAPSR_NZCVQG: + v7m_msr_xpsr(env, 0b1100, 1, *(uint32_t *)value); + break; + case UC_ARM_REG_EAPSR: + case UC_ARM_REG_EAPSR_NZCVQ: + v7m_msr_xpsr(env, 0b1000, 2, *(uint32_t *)value); + break; + case UC_ARM_REG_EAPSR_G: + v7m_msr_xpsr(env, 0b0100, 2, *(uint32_t *)value); + break; + case UC_ARM_REG_EAPSR_NZCVQG: + v7m_msr_xpsr(env, 0b1100, 2, *(uint32_t *)value); + break; + case UC_ARM_REG_XPSR: + case UC_ARM_REG_XPSR_NZCVQ: + v7m_msr_xpsr(env, 0b1000, 3, *(uint32_t *)value); + break; + case UC_ARM_REG_XPSR_G: + v7m_msr_xpsr(env, 0b0100, 3, *(uint32_t *)value); + break; + case UC_ARM_REG_XPSR_NZCVQG: + v7m_msr_xpsr(env, 0b1100, 3, *(uint32_t *)value); + break; } } return; } -int arm_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int count) +int arm_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, + int count) { CPUARMState *env = &(ARM_CPU(uc->cpu)->env); int i; @@ -375,7 +381,8 @@ int arm_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int coun return 0; } -int arm_reg_write(struct uc_struct *uc, unsigned int *regs, void* const* vals, int count) +int arm_reg_write(struct uc_struct *uc, unsigned int *regs, void *const *vals, + int count) { CPUArchState *env = &(ARM_CPU(uc->cpu)->env); int i; @@ -384,7 +391,7 @@ int arm_reg_write(struct uc_struct *uc, unsigned int *regs, void* const* vals, i unsigned int regid = regs[i]; const void *value = vals[i]; reg_write(env, regid, value); - if(regid == UC_ARM_REG_R15){ + if (regid == UC_ARM_REG_R15) { // force to quit execution and flush TB uc->quit_request = true; uc_emu_stop(uc); @@ -396,9 +403,11 @@ int arm_reg_write(struct uc_struct *uc, unsigned int *regs, void* const* vals, i DEFAULT_VISIBILITY #ifdef TARGET_WORDS_BIGENDIAN -int armeb_context_reg_read(struct uc_context *ctx, unsigned int *regs, void **vals, int count) +int armeb_context_reg_read(struct uc_context *ctx, unsigned int *regs, + void **vals, int count) #else -int arm_context_reg_read(struct uc_context *ctx, unsigned int *regs, void **vals, int count) +int arm_context_reg_read(struct uc_context *ctx, unsigned int *regs, + void **vals, int count) #endif { CPUARMState *env = (CPUARMState *)ctx->data; @@ -415,9 +424,11 @@ int arm_context_reg_read(struct uc_context *ctx, unsigned int *regs, void **vals DEFAULT_VISIBILITY #ifdef TARGET_WORDS_BIGENDIAN -int armeb_context_reg_write(struct uc_context *ctx, unsigned int *regs, void* const* vals, int count) +int armeb_context_reg_write(struct uc_context *ctx, unsigned int *regs, + void *const *vals, int count) #else -int arm_context_reg_write(struct uc_context *ctx, unsigned int *regs, void* const* vals, int count) +int arm_context_reg_write(struct uc_context *ctx, unsigned int *regs, + void *const *vals, int count) #endif { CPUARMState *env = (CPUARMState *)ctx->data; @@ -434,33 +445,35 @@ int arm_context_reg_write(struct uc_context *ctx, unsigned int *regs, void* cons static bool arm_stop_interrupt(struct uc_struct *uc, int intno) { - switch(intno) { - default: - return false; - case EXCP_UDEF: - case EXCP_YIELD: - return true; - case EXCP_INVSTATE: - uc->invalid_error = UC_ERR_EXCEPTION; - return true; + switch (intno) { + default: + return false; + case EXCP_UDEF: + case EXCP_YIELD: + return true; + case EXCP_INVSTATE: + uc->invalid_error = UC_ERR_EXCEPTION; + return true; } } -static uc_err arm_query(struct uc_struct *uc, uc_query_type type, size_t *result) +static uc_err arm_query(struct uc_struct *uc, uc_query_type type, + size_t *result) { CPUState *mycpu = uc->cpu; uint32_t mode; - switch(type) { - case UC_QUERY_MODE: - // zero out ARM/THUMB mode - mode = uc->mode & ~(UC_MODE_ARM | UC_MODE_THUMB); - // THUMB mode or ARM MOde - mode += ((ARM_CPU(mycpu)->env.thumb != 0)? UC_MODE_THUMB : UC_MODE_ARM); - *result = mode; - return UC_ERR_OK; - default: - return UC_ERR_ARG; + switch (type) { + case UC_QUERY_MODE: + // zero out ARM/THUMB mode + mode = uc->mode & ~(UC_MODE_ARM | UC_MODE_THUMB); + // THUMB mode or ARM MOde + mode += + ((ARM_CPU(mycpu)->env.thumb != 0) ? UC_MODE_THUMB : UC_MODE_ARM); + *result = mode; + return UC_ERR_OK; + default: + return UC_ERR_ARG; } } @@ -477,9 +490,9 @@ static int arm_cpus_init(struct uc_struct *uc, const char *cpu_model) } #ifdef TARGET_WORDS_BIGENDIAN -void armeb_uc_init(struct uc_struct* uc) +void armeb_uc_init(struct uc_struct *uc) #else -void arm_uc_init(struct uc_struct* uc) +void arm_uc_init(struct uc_struct *uc) #endif { uc->reg_read = arm_reg_read;