Format unicorn_arm and unicorn_aarch64
This commit is contained in:
parent
0a3e46bf4f
commit
6c3960242b
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@ -5,4 +5,4 @@ find ./msvc -maxdepth 1 "(" -name "*.c" -or -name "*.h" ")" -exec clang-format -
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find ./include -maxdepth 2 "(" -name "*.c" -or -name "*.h" ")" -exec clang-format -i -style=file "{}" ";"
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find ./include -maxdepth 2 "(" -name "*.c" -or -name "*.h" ")" -exec clang-format -i -style=file "{}" ";"
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find ./tests/unit -maxdepth 1 "(" -name "*.c" -or -name "*.h" ")" -exec clang-format -i -style=file "{}" ";"
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find ./tests/unit -maxdepth 1 "(" -name "*.c" -or -name "*.h" ")" -exec clang-format -i -style=file "{}" ";"
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find ./samples -maxdepth 1 "(" -name "*.c" -or -name "*.h" ")" -exec clang-format -i -style=file "{}" ";"
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find ./samples -maxdepth 1 "(" -name "*.c" -or -name "*.h" ")" -exec clang-format -i -style=file "{}" ";"
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find ./qemu "(" -name "unicorn.c" -or -name "unicorn.h" ")" -exec clang-format -i -style=file "{}" ";"
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find ./qemu "(" -name "unicorn.c" -or -name "unicorn.h" -or -name "unicorn_arm.c" -or -name "unicorn_aarch64.c" ")" -exec clang-format -i -style=file "{}" ";"
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@ -17,7 +17,7 @@ static void arm64_set_pc(struct uc_struct *uc, uint64_t address)
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((CPUARMState *)uc->cpu->env_ptr)->pc = address;
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((CPUARMState *)uc->cpu->env_ptr)->pc = address;
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}
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}
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static void arm64_release(void* ctx)
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static void arm64_release(void *ctx)
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{
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{
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int i;
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int i;
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TCGContext *tcg_ctx = (TCGContext *)ctx;
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TCGContext *tcg_ctx = (TCGContext *)ctx;
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@ -38,11 +38,13 @@ static void arm64_release(void* ctx)
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g_free(fast->table);
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g_free(fast->table);
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}
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}
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QLIST_FOREACH_SAFE(entry, &cpu->pre_el_change_hooks, node, next) {
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QLIST_FOREACH_SAFE(entry, &cpu->pre_el_change_hooks, node, next)
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{
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QLIST_SAFE_REMOVE(entry, node);
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QLIST_SAFE_REMOVE(entry, node);
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g_free(entry);
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g_free(entry);
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}
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}
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QLIST_FOREACH_SAFE(entry, &cpu->el_change_hooks, node, next) {
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QLIST_FOREACH_SAFE(entry, &cpu->el_change_hooks, node, next)
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{
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QLIST_SAFE_REMOVE(entry, node);
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QLIST_SAFE_REMOVE(entry, node);
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g_free(entry);
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g_free(entry);
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}
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}
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@ -98,31 +100,36 @@ static void reg_read(CPUARMState *env, unsigned int regid, void *value)
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} else if (regid >= UC_ARM64_REG_W0 && regid <= UC_ARM64_REG_W30) {
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} else if (regid >= UC_ARM64_REG_W0 && regid <= UC_ARM64_REG_W30) {
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*(int32_t *)value = READ_DWORD(env->xregs[regid - UC_ARM64_REG_W0]);
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*(int32_t *)value = READ_DWORD(env->xregs[regid - UC_ARM64_REG_W0]);
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} else if (regid >= UC_ARM64_REG_Q0 && regid <= UC_ARM64_REG_Q31) { // FIXME
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} else if (regid >= UC_ARM64_REG_Q0 && regid <= UC_ARM64_REG_Q31) { // FIXME
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float64 *dst = (float64*) value;
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float64 *dst = (float64 *)value;
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uint32_t reg_index = regid - UC_ARM64_REG_Q0;
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uint32_t reg_index = regid - UC_ARM64_REG_Q0;
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dst[0] = env->vfp.zregs[reg_index].d[0];
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dst[0] = env->vfp.zregs[reg_index].d[0];
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dst[1] = env->vfp.zregs[reg_index].d[1];
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dst[1] = env->vfp.zregs[reg_index].d[1];
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} else if (regid >= UC_ARM64_REG_D0 && regid <= UC_ARM64_REG_D31) {
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} else if (regid >= UC_ARM64_REG_D0 && regid <= UC_ARM64_REG_D31) {
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*(float64*)value = env->vfp.zregs[regid - UC_ARM64_REG_D0].d[0];
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*(float64 *)value = env->vfp.zregs[regid - UC_ARM64_REG_D0].d[0];
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} else if (regid >= UC_ARM64_REG_S0 && regid <= UC_ARM64_REG_S31) {
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} else if (regid >= UC_ARM64_REG_S0 && regid <= UC_ARM64_REG_S31) {
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*(int32_t*)value = READ_DWORD(env->vfp.zregs[regid - UC_ARM64_REG_S0].d[0]);
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*(int32_t *)value =
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READ_DWORD(env->vfp.zregs[regid - UC_ARM64_REG_S0].d[0]);
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} else if (regid >= UC_ARM64_REG_H0 && regid <= UC_ARM64_REG_H31) {
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} else if (regid >= UC_ARM64_REG_H0 && regid <= UC_ARM64_REG_H31) {
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*(int16_t*)value = READ_WORD(env->vfp.zregs[regid - UC_ARM64_REG_H0].d[0]);
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*(int16_t *)value =
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READ_WORD(env->vfp.zregs[regid - UC_ARM64_REG_H0].d[0]);
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} else if (regid >= UC_ARM64_REG_B0 && regid <= UC_ARM64_REG_B31) {
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} else if (regid >= UC_ARM64_REG_B0 && regid <= UC_ARM64_REG_B31) {
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*(int8_t*)value = READ_BYTE_L(env->vfp.zregs[regid - UC_ARM64_REG_B0].d[0]);
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*(int8_t *)value =
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READ_BYTE_L(env->vfp.zregs[regid - UC_ARM64_REG_B0].d[0]);
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} else if (regid >= UC_ARM64_REG_ELR_EL0 && regid <= UC_ARM64_REG_ELR_EL3) {
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} else if (regid >= UC_ARM64_REG_ELR_EL0 && regid <= UC_ARM64_REG_ELR_EL3) {
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*(uint64_t*)value = env->elr_el[regid - UC_ARM64_REG_ELR_EL0];
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*(uint64_t *)value = env->elr_el[regid - UC_ARM64_REG_ELR_EL0];
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} else if (regid >= UC_ARM64_REG_SP_EL0 && regid <= UC_ARM64_REG_SP_EL3) {
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} else if (regid >= UC_ARM64_REG_SP_EL0 && regid <= UC_ARM64_REG_SP_EL3) {
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*(uint64_t*)value = env->sp_el[regid - UC_ARM64_REG_SP_EL0];
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*(uint64_t *)value = env->sp_el[regid - UC_ARM64_REG_SP_EL0];
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} else if (regid >= UC_ARM64_REG_ESR_EL0 && regid <= UC_ARM64_REG_ESR_EL3) {
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} else if (regid >= UC_ARM64_REG_ESR_EL0 && regid <= UC_ARM64_REG_ESR_EL3) {
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*(uint64_t*)value = env->cp15.esr_el[regid - UC_ARM64_REG_ESR_EL0];
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*(uint64_t *)value = env->cp15.esr_el[regid - UC_ARM64_REG_ESR_EL0];
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} else if (regid >= UC_ARM64_REG_FAR_EL0 && regid <= UC_ARM64_REG_FAR_EL3) {
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} else if (regid >= UC_ARM64_REG_FAR_EL0 && regid <= UC_ARM64_REG_FAR_EL3) {
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*(uint64_t*)value = env->cp15.far_el[regid - UC_ARM64_REG_FAR_EL0];
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*(uint64_t *)value = env->cp15.far_el[regid - UC_ARM64_REG_FAR_EL0];
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} else if (regid >= UC_ARM64_REG_VBAR_EL0 && regid <= UC_ARM64_REG_VBAR_EL3) {
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} else if (regid >= UC_ARM64_REG_VBAR_EL0 &&
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*(uint64_t*)value = env->cp15.vbar_el[regid - UC_ARM64_REG_VBAR_EL0];
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regid <= UC_ARM64_REG_VBAR_EL3) {
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*(uint64_t *)value = env->cp15.vbar_el[regid - UC_ARM64_REG_VBAR_EL0];
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} else {
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} else {
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switch(regid) {
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switch (regid) {
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default: break;
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default:
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break;
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case UC_ARM64_REG_CPACR_EL1:
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case UC_ARM64_REG_CPACR_EL1:
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// *(uint32_t *)value = env->cp15.c1_coproc;
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// *(uint32_t *)value = env->cp15.c1_coproc;
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break;
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break;
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@ -181,42 +188,47 @@ static void reg_write(CPUARMState *env, unsigned int regid, const void *value)
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} else if (regid >= UC_ARM64_REG_W0 && regid <= UC_ARM64_REG_W30) {
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} else if (regid >= UC_ARM64_REG_W0 && regid <= UC_ARM64_REG_W30) {
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WRITE_DWORD(env->xregs[regid - UC_ARM64_REG_W0], *(uint32_t *)value);
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WRITE_DWORD(env->xregs[regid - UC_ARM64_REG_W0], *(uint32_t *)value);
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} else if (regid >= UC_ARM64_REG_Q0 && regid <= UC_ARM64_REG_Q31) {
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} else if (regid >= UC_ARM64_REG_Q0 && regid <= UC_ARM64_REG_Q31) {
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float64 *src = (float64*) value;
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float64 *src = (float64 *)value;
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uint32_t reg_index = regid - UC_ARM64_REG_Q0;
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uint32_t reg_index = regid - UC_ARM64_REG_Q0;
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env->vfp.zregs[reg_index].d[0] = src[0];
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env->vfp.zregs[reg_index].d[0] = src[0];
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env->vfp.zregs[reg_index].d[1] = src[1];
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env->vfp.zregs[reg_index].d[1] = src[1];
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} else if (regid >= UC_ARM64_REG_D0 && regid <= UC_ARM64_REG_D31) {
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} else if (regid >= UC_ARM64_REG_D0 && regid <= UC_ARM64_REG_D31) {
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env->vfp.zregs[regid - UC_ARM64_REG_D0].d[0] = * (float64*) value;
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env->vfp.zregs[regid - UC_ARM64_REG_D0].d[0] = *(float64 *)value;
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} else if (regid >= UC_ARM64_REG_S0 && regid <= UC_ARM64_REG_S31) {
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} else if (regid >= UC_ARM64_REG_S0 && regid <= UC_ARM64_REG_S31) {
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WRITE_DWORD(env->vfp.zregs[regid - UC_ARM64_REG_S0].d[0], *(int32_t*) value);
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WRITE_DWORD(env->vfp.zregs[regid - UC_ARM64_REG_S0].d[0],
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*(int32_t *)value);
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} else if (regid >= UC_ARM64_REG_H0 && regid <= UC_ARM64_REG_H31) {
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} else if (regid >= UC_ARM64_REG_H0 && regid <= UC_ARM64_REG_H31) {
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WRITE_WORD(env->vfp.zregs[regid - UC_ARM64_REG_H0].d[0], *(int16_t*) value);
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WRITE_WORD(env->vfp.zregs[regid - UC_ARM64_REG_H0].d[0],
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*(int16_t *)value);
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} else if (regid >= UC_ARM64_REG_B0 && regid <= UC_ARM64_REG_B31) {
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} else if (regid >= UC_ARM64_REG_B0 && regid <= UC_ARM64_REG_B31) {
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WRITE_BYTE_L(env->vfp.zregs[regid - UC_ARM64_REG_B0].d[0], *(int8_t*) value);
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WRITE_BYTE_L(env->vfp.zregs[regid - UC_ARM64_REG_B0].d[0],
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*(int8_t *)value);
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} else if (regid >= UC_ARM64_REG_ELR_EL0 && regid <= UC_ARM64_REG_ELR_EL3) {
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} else if (regid >= UC_ARM64_REG_ELR_EL0 && regid <= UC_ARM64_REG_ELR_EL3) {
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env->elr_el[regid - UC_ARM64_REG_ELR_EL0] = *(uint64_t*)value;
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env->elr_el[regid - UC_ARM64_REG_ELR_EL0] = *(uint64_t *)value;
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} else if (regid >= UC_ARM64_REG_SP_EL0 && regid <= UC_ARM64_REG_SP_EL3) {
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} else if (regid >= UC_ARM64_REG_SP_EL0 && regid <= UC_ARM64_REG_SP_EL3) {
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env->sp_el[regid - UC_ARM64_REG_SP_EL0] = *(uint64_t*)value;
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env->sp_el[regid - UC_ARM64_REG_SP_EL0] = *(uint64_t *)value;
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} else if (regid >= UC_ARM64_REG_ESR_EL0 && regid <= UC_ARM64_REG_ESR_EL3) {
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} else if (regid >= UC_ARM64_REG_ESR_EL0 && regid <= UC_ARM64_REG_ESR_EL3) {
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env->cp15.esr_el[regid - UC_ARM64_REG_ESR_EL0] = *(uint64_t*)value;
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env->cp15.esr_el[regid - UC_ARM64_REG_ESR_EL0] = *(uint64_t *)value;
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} else if (regid >= UC_ARM64_REG_FAR_EL0 && regid <= UC_ARM64_REG_FAR_EL3) {
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} else if (regid >= UC_ARM64_REG_FAR_EL0 && regid <= UC_ARM64_REG_FAR_EL3) {
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env->cp15.far_el[regid - UC_ARM64_REG_FAR_EL0] = *(uint64_t*)value;
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env->cp15.far_el[regid - UC_ARM64_REG_FAR_EL0] = *(uint64_t *)value;
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} else if (regid >= UC_ARM64_REG_VBAR_EL0 && regid <= UC_ARM64_REG_VBAR_EL3) {
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} else if (regid >= UC_ARM64_REG_VBAR_EL0 &&
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env->cp15.vbar_el[regid - UC_ARM64_REG_VBAR_EL0] = *(uint64_t*)value;
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regid <= UC_ARM64_REG_VBAR_EL3) {
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env->cp15.vbar_el[regid - UC_ARM64_REG_VBAR_EL0] = *(uint64_t *)value;
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} else {
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} else {
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switch(regid) {
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switch (regid) {
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default: break;
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default:
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break;
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case UC_ARM64_REG_CPACR_EL1:
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case UC_ARM64_REG_CPACR_EL1:
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//env->cp15.c1_coproc = *(uint32_t *)value;
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// env->cp15.c1_coproc = *(uint32_t *)value;
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break;
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break;
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case UC_ARM64_REG_TPIDR_EL0:
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case UC_ARM64_REG_TPIDR_EL0:
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//env->cp15.tpidr_el0 = *(uint64_t *)value;
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// env->cp15.tpidr_el0 = *(uint64_t *)value;
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break;
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break;
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case UC_ARM64_REG_TPIDRRO_EL0:
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case UC_ARM64_REG_TPIDRRO_EL0:
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//env->cp15.tpidrro_el0 = *(uint64_t *)value;
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// env->cp15.tpidrro_el0 = *(uint64_t *)value;
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break;
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break;
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case UC_ARM64_REG_TPIDR_EL1:
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case UC_ARM64_REG_TPIDR_EL1:
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//env->cp15.tpidr_el1 = *(uint64_t *)value;
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// env->cp15.tpidr_el1 = *(uint64_t *)value;
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break;
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break;
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case UC_ARM64_REG_X29:
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case UC_ARM64_REG_X29:
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env->xregs[29] = *(uint64_t *)value;
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env->xregs[29] = *(uint64_t *)value;
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@ -231,22 +243,22 @@ static void reg_write(CPUARMState *env, unsigned int regid, const void *value)
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env->xregs[31] = *(uint64_t *)value;
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env->xregs[31] = *(uint64_t *)value;
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break;
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break;
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case UC_ARM64_REG_NZCV:
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case UC_ARM64_REG_NZCV:
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//cpsr_write(env, *(uint32_t *)value, CPSR_NZCV);
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// cpsr_write(env, *(uint32_t *)value, CPSR_NZCV);
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break;
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break;
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case UC_ARM64_REG_PSTATE:
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case UC_ARM64_REG_PSTATE:
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pstate_write(env, *(uint32_t *)value);
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pstate_write(env, *(uint32_t *)value);
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break;
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break;
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case UC_ARM64_REG_TTBR0_EL1:
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case UC_ARM64_REG_TTBR0_EL1:
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//env->cp15.ttbr0_el1 = *(uint64_t *)value;
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// env->cp15.ttbr0_el1 = *(uint64_t *)value;
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break;
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break;
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case UC_ARM64_REG_TTBR1_EL1:
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case UC_ARM64_REG_TTBR1_EL1:
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//env->cp15.ttbr1_el1 = *(uint64_t *)value;
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// env->cp15.ttbr1_el1 = *(uint64_t *)value;
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break;
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break;
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case UC_ARM64_REG_PAR_EL1:
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case UC_ARM64_REG_PAR_EL1:
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//env->cp15.par_el1 = *(uint64_t *)value;
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// env->cp15.par_el1 = *(uint64_t *)value;
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break;
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break;
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case UC_ARM64_REG_MAIR_EL1:
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case UC_ARM64_REG_MAIR_EL1:
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//env->cp15.mair_el1 = *(uint64_t *)value;
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// env->cp15.mair_el1 = *(uint64_t *)value;
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break;
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break;
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}
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}
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}
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}
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@ -254,9 +266,10 @@ static void reg_write(CPUARMState *env, unsigned int regid, const void *value)
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return;
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return;
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}
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}
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int arm64_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int count)
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int arm64_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals,
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int count)
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{
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{
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CPUARMState *env= &(ARM_CPU(uc->cpu)->env);
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CPUARMState *env = &(ARM_CPU(uc->cpu)->env);
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int i;
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int i;
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for (i = 0; i < count; i++) {
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for (i = 0; i < count; i++) {
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@ -268,16 +281,17 @@ int arm64_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int co
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return 0;
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return 0;
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}
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}
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int arm64_reg_write(struct uc_struct *uc, unsigned int *regs, void* const* vals, int count)
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int arm64_reg_write(struct uc_struct *uc, unsigned int *regs, void *const *vals,
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int count)
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{
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{
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CPUARMState *env= &(ARM_CPU(uc->cpu)->env);
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CPUARMState *env = &(ARM_CPU(uc->cpu)->env);
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int i;
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int i;
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for (i = 0; i < count; i++) {
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for (i = 0; i < count; i++) {
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unsigned int regid = regs[i];
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unsigned int regid = regs[i];
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const void *value = vals[i];
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const void *value = vals[i];
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reg_write(env, regid, value);
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reg_write(env, regid, value);
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if(regid == UC_ARM64_REG_PC){
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if (regid == UC_ARM64_REG_PC) {
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// force to quit execution and flush TB
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// force to quit execution and flush TB
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uc->quit_request = true;
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uc->quit_request = true;
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uc_emu_stop(uc);
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uc_emu_stop(uc);
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@ -289,12 +303,14 @@ int arm64_reg_write(struct uc_struct *uc, unsigned int *regs, void* const* vals,
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DEFAULT_VISIBILITY
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DEFAULT_VISIBILITY
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#ifdef TARGET_WORDS_BIGENDIAN
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#ifdef TARGET_WORDS_BIGENDIAN
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int arm64eb_context_reg_read(struct uc_context *ctx, unsigned int *regs, void **vals, int count)
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int arm64eb_context_reg_read(struct uc_context *ctx, unsigned int *regs,
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void **vals, int count)
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#else
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#else
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int arm64_context_reg_read(struct uc_context *ctx, unsigned int *regs, void **vals, int count)
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int arm64_context_reg_read(struct uc_context *ctx, unsigned int *regs,
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void **vals, int count)
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#endif
|
#endif
|
||||||
{
|
{
|
||||||
CPUARMState *env= (CPUARMState *)ctx->data;
|
CPUARMState *env = (CPUARMState *)ctx->data;
|
||||||
int i;
|
int i;
|
||||||
|
|
||||||
for (i = 0; i < count; i++) {
|
for (i = 0; i < count; i++) {
|
||||||
|
@ -308,12 +324,14 @@ int arm64_context_reg_read(struct uc_context *ctx, unsigned int *regs, void **va
|
||||||
|
|
||||||
DEFAULT_VISIBILITY
|
DEFAULT_VISIBILITY
|
||||||
#ifdef TARGET_WORDS_BIGENDIAN
|
#ifdef TARGET_WORDS_BIGENDIAN
|
||||||
int arm64eb_context_reg_write(struct uc_context *ctx, unsigned int *regs, void* const* vals, int count)
|
int arm64eb_context_reg_write(struct uc_context *ctx, unsigned int *regs,
|
||||||
|
void *const *vals, int count)
|
||||||
#else
|
#else
|
||||||
int arm64_context_reg_write(struct uc_context *ctx, unsigned int *regs, void* const* vals, int count)
|
int arm64_context_reg_write(struct uc_context *ctx, unsigned int *regs,
|
||||||
|
void *const *vals, int count)
|
||||||
#endif
|
#endif
|
||||||
{
|
{
|
||||||
CPUARMState *env= (CPUARMState *)ctx->data;
|
CPUARMState *env = (CPUARMState *)ctx->data;
|
||||||
int i;
|
int i;
|
||||||
|
|
||||||
for (i = 0; i < count; i++) {
|
for (i = 0; i < count; i++) {
|
||||||
|
@ -339,9 +357,9 @@ static int arm64_cpus_init(struct uc_struct *uc, const char *cpu_model)
|
||||||
|
|
||||||
DEFAULT_VISIBILITY
|
DEFAULT_VISIBILITY
|
||||||
#ifdef TARGET_WORDS_BIGENDIAN
|
#ifdef TARGET_WORDS_BIGENDIAN
|
||||||
void arm64eb_uc_init(struct uc_struct* uc)
|
void arm64eb_uc_init(struct uc_struct *uc)
|
||||||
#else
|
#else
|
||||||
void arm64_uc_init(struct uc_struct* uc)
|
void arm64_uc_init(struct uc_struct *uc)
|
||||||
#endif
|
#endif
|
||||||
{
|
{
|
||||||
uc->reg_read = arm64_reg_read;
|
uc->reg_read = arm64_reg_read;
|
||||||
|
|
|
@ -23,7 +23,7 @@ static void arm_release(void *ctx)
|
||||||
{
|
{
|
||||||
int i;
|
int i;
|
||||||
TCGContext *tcg_ctx = (TCGContext *)ctx;
|
TCGContext *tcg_ctx = (TCGContext *)ctx;
|
||||||
ARMCPU* cpu = (ARMCPU *)tcg_ctx->uc->cpu;
|
ARMCPU *cpu = (ARMCPU *)tcg_ctx->uc->cpu;
|
||||||
CPUTLBDesc *d = cpu->neg.tlb.d;
|
CPUTLBDesc *d = cpu->neg.tlb.d;
|
||||||
CPUTLBDescFast *f = cpu->neg.tlb.f;
|
CPUTLBDescFast *f = cpu->neg.tlb.f;
|
||||||
CPUTLBDesc *desc;
|
CPUTLBDesc *desc;
|
||||||
|
@ -40,11 +40,13 @@ static void arm_release(void *ctx)
|
||||||
g_free(fast->table);
|
g_free(fast->table);
|
||||||
}
|
}
|
||||||
|
|
||||||
QLIST_FOREACH_SAFE(entry, &cpu->pre_el_change_hooks, node, next) {
|
QLIST_FOREACH_SAFE(entry, &cpu->pre_el_change_hooks, node, next)
|
||||||
|
{
|
||||||
QLIST_SAFE_REMOVE(entry, node);
|
QLIST_SAFE_REMOVE(entry, node);
|
||||||
g_free(entry);
|
g_free(entry);
|
||||||
}
|
}
|
||||||
QLIST_FOREACH_SAFE(entry, &cpu->el_change_hooks, node, next) {
|
QLIST_FOREACH_SAFE(entry, &cpu->el_change_hooks, node, next)
|
||||||
|
{
|
||||||
QLIST_SAFE_REMOVE(entry, node);
|
QLIST_SAFE_REMOVE(entry, node);
|
||||||
g_free(entry);
|
g_free(entry);
|
||||||
}
|
}
|
||||||
|
@ -120,7 +122,8 @@ static uint32_t v7m_mrs_xpsr(CPUARMState *env, uint32_t reg)
|
||||||
return xpsr_read(env) & mask;
|
return xpsr_read(env) & mask;
|
||||||
}
|
}
|
||||||
|
|
||||||
static void v7m_msr_xpsr(CPUARMState *env, uint32_t mask, uint32_t reg, uint32_t val)
|
static void v7m_msr_xpsr(CPUARMState *env, uint32_t mask, uint32_t reg,
|
||||||
|
uint32_t val)
|
||||||
{
|
{
|
||||||
uint32_t xpsrmask = 0;
|
uint32_t xpsrmask = 0;
|
||||||
|
|
||||||
|
@ -152,12 +155,13 @@ static void reg_read(CPUARMState *env, unsigned int regid, void *value)
|
||||||
uint32_t reg_index = regid - UC_ARM_REG_D0;
|
uint32_t reg_index = regid - UC_ARM_REG_D0;
|
||||||
*(float64 *)value = env->vfp.zregs[reg_index / 2].d[reg_index & 1];
|
*(float64 *)value = env->vfp.zregs[reg_index / 2].d[reg_index & 1];
|
||||||
} else {
|
} else {
|
||||||
switch(regid) {
|
switch (regid) {
|
||||||
case UC_ARM_REG_APSR:
|
case UC_ARM_REG_APSR:
|
||||||
if (arm_feature(env, ARM_FEATURE_M)) {
|
if (arm_feature(env, ARM_FEATURE_M)) {
|
||||||
*(int32_t *)value = v7m_mrs_xpsr(env, 0);
|
*(int32_t *)value = v7m_mrs_xpsr(env, 0);
|
||||||
} else {
|
} else {
|
||||||
*(int32_t *)value = cpsr_read(env) & (CPSR_NZCV | CPSR_Q | CPSR_GE);
|
*(int32_t *)value =
|
||||||
|
cpsr_read(env) & (CPSR_NZCV | CPSR_Q | CPSR_GE);
|
||||||
}
|
}
|
||||||
break;
|
break;
|
||||||
case UC_ARM_REG_APSR_NZCV:
|
case UC_ARM_REG_APSR_NZCV:
|
||||||
|
@ -169,15 +173,15 @@ static void reg_read(CPUARMState *env, unsigned int regid, void *value)
|
||||||
case UC_ARM_REG_SPSR:
|
case UC_ARM_REG_SPSR:
|
||||||
*(int32_t *)value = env->spsr;
|
*(int32_t *)value = env->spsr;
|
||||||
break;
|
break;
|
||||||
//case UC_ARM_REG_SP:
|
// case UC_ARM_REG_SP:
|
||||||
case UC_ARM_REG_R13:
|
case UC_ARM_REG_R13:
|
||||||
*(int32_t *)value = env->regs[13];
|
*(int32_t *)value = env->regs[13];
|
||||||
break;
|
break;
|
||||||
//case UC_ARM_REG_LR:
|
// case UC_ARM_REG_LR:
|
||||||
case UC_ARM_REG_R14:
|
case UC_ARM_REG_R14:
|
||||||
*(int32_t *)value = env->regs[14];
|
*(int32_t *)value = env->regs[14];
|
||||||
break;
|
break;
|
||||||
//case UC_ARM_REG_PC:
|
// case UC_ARM_REG_PC:
|
||||||
case UC_ARM_REG_R15:
|
case UC_ARM_REG_R15:
|
||||||
*(int32_t *)value = env->regs[15];
|
*(int32_t *)value = env->regs[15];
|
||||||
break;
|
break;
|
||||||
|
@ -243,10 +247,11 @@ static void reg_write(CPUARMState *env, unsigned int regid, const void *value)
|
||||||
uint32_t reg_index = regid - UC_ARM_REG_D0;
|
uint32_t reg_index = regid - UC_ARM_REG_D0;
|
||||||
env->vfp.zregs[reg_index / 2].d[reg_index & 1] = *(float64 *)value;
|
env->vfp.zregs[reg_index / 2].d[reg_index & 1] = *(float64 *)value;
|
||||||
} else {
|
} else {
|
||||||
switch(regid) {
|
switch (regid) {
|
||||||
case UC_ARM_REG_APSR:
|
case UC_ARM_REG_APSR:
|
||||||
if (!arm_feature(env, ARM_FEATURE_M)) {
|
if (!arm_feature(env, ARM_FEATURE_M)) {
|
||||||
cpsr_write(env, *(uint32_t *)value, (CPSR_NZCV | CPSR_Q | CPSR_GE), CPSRWriteRaw);
|
cpsr_write(env, *(uint32_t *)value,
|
||||||
|
(CPSR_NZCV | CPSR_Q | CPSR_GE), CPSRWriteRaw);
|
||||||
} else {
|
} else {
|
||||||
// Same with UC_ARM_REG_APSR_NZCVQ
|
// Same with UC_ARM_REG_APSR_NZCVQ
|
||||||
v7m_msr_xpsr(env, 0b1000, 0, *(uint32_t *)value);
|
v7m_msr_xpsr(env, 0b1000, 0, *(uint32_t *)value);
|
||||||
|
@ -261,15 +266,15 @@ static void reg_write(CPUARMState *env, unsigned int regid, const void *value)
|
||||||
case UC_ARM_REG_SPSR:
|
case UC_ARM_REG_SPSR:
|
||||||
env->spsr = *(uint32_t *)value;
|
env->spsr = *(uint32_t *)value;
|
||||||
break;
|
break;
|
||||||
//case UC_ARM_REG_SP:
|
// case UC_ARM_REG_SP:
|
||||||
case UC_ARM_REG_R13:
|
case UC_ARM_REG_R13:
|
||||||
env->regs[13] = *(uint32_t *)value;
|
env->regs[13] = *(uint32_t *)value;
|
||||||
break;
|
break;
|
||||||
//case UC_ARM_REG_LR:
|
// case UC_ARM_REG_LR:
|
||||||
case UC_ARM_REG_R14:
|
case UC_ARM_REG_R14:
|
||||||
env->regs[14] = *(uint32_t *)value;
|
env->regs[14] = *(uint32_t *)value;
|
||||||
break;
|
break;
|
||||||
//case UC_ARM_REG_PC:
|
// case UC_ARM_REG_PC:
|
||||||
case UC_ARM_REG_R15:
|
case UC_ARM_REG_R15:
|
||||||
env->pc = (*(uint32_t *)value & ~1);
|
env->pc = (*(uint32_t *)value & ~1);
|
||||||
env->thumb = (*(uint32_t *)value & 1);
|
env->thumb = (*(uint32_t *)value & 1);
|
||||||
|
@ -361,7 +366,8 @@ static void reg_write(CPUARMState *env, unsigned int regid, const void *value)
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
int arm_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int count)
|
int arm_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals,
|
||||||
|
int count)
|
||||||
{
|
{
|
||||||
CPUARMState *env = &(ARM_CPU(uc->cpu)->env);
|
CPUARMState *env = &(ARM_CPU(uc->cpu)->env);
|
||||||
int i;
|
int i;
|
||||||
|
@ -375,7 +381,8 @@ int arm_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int coun
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
int arm_reg_write(struct uc_struct *uc, unsigned int *regs, void* const* vals, int count)
|
int arm_reg_write(struct uc_struct *uc, unsigned int *regs, void *const *vals,
|
||||||
|
int count)
|
||||||
{
|
{
|
||||||
CPUArchState *env = &(ARM_CPU(uc->cpu)->env);
|
CPUArchState *env = &(ARM_CPU(uc->cpu)->env);
|
||||||
int i;
|
int i;
|
||||||
|
@ -384,7 +391,7 @@ int arm_reg_write(struct uc_struct *uc, unsigned int *regs, void* const* vals, i
|
||||||
unsigned int regid = regs[i];
|
unsigned int regid = regs[i];
|
||||||
const void *value = vals[i];
|
const void *value = vals[i];
|
||||||
reg_write(env, regid, value);
|
reg_write(env, regid, value);
|
||||||
if(regid == UC_ARM_REG_R15){
|
if (regid == UC_ARM_REG_R15) {
|
||||||
// force to quit execution and flush TB
|
// force to quit execution and flush TB
|
||||||
uc->quit_request = true;
|
uc->quit_request = true;
|
||||||
uc_emu_stop(uc);
|
uc_emu_stop(uc);
|
||||||
|
@ -396,9 +403,11 @@ int arm_reg_write(struct uc_struct *uc, unsigned int *regs, void* const* vals, i
|
||||||
|
|
||||||
DEFAULT_VISIBILITY
|
DEFAULT_VISIBILITY
|
||||||
#ifdef TARGET_WORDS_BIGENDIAN
|
#ifdef TARGET_WORDS_BIGENDIAN
|
||||||
int armeb_context_reg_read(struct uc_context *ctx, unsigned int *regs, void **vals, int count)
|
int armeb_context_reg_read(struct uc_context *ctx, unsigned int *regs,
|
||||||
|
void **vals, int count)
|
||||||
#else
|
#else
|
||||||
int arm_context_reg_read(struct uc_context *ctx, unsigned int *regs, void **vals, int count)
|
int arm_context_reg_read(struct uc_context *ctx, unsigned int *regs,
|
||||||
|
void **vals, int count)
|
||||||
#endif
|
#endif
|
||||||
{
|
{
|
||||||
CPUARMState *env = (CPUARMState *)ctx->data;
|
CPUARMState *env = (CPUARMState *)ctx->data;
|
||||||
|
@ -415,9 +424,11 @@ int arm_context_reg_read(struct uc_context *ctx, unsigned int *regs, void **vals
|
||||||
|
|
||||||
DEFAULT_VISIBILITY
|
DEFAULT_VISIBILITY
|
||||||
#ifdef TARGET_WORDS_BIGENDIAN
|
#ifdef TARGET_WORDS_BIGENDIAN
|
||||||
int armeb_context_reg_write(struct uc_context *ctx, unsigned int *regs, void* const* vals, int count)
|
int armeb_context_reg_write(struct uc_context *ctx, unsigned int *regs,
|
||||||
|
void *const *vals, int count)
|
||||||
#else
|
#else
|
||||||
int arm_context_reg_write(struct uc_context *ctx, unsigned int *regs, void* const* vals, int count)
|
int arm_context_reg_write(struct uc_context *ctx, unsigned int *regs,
|
||||||
|
void *const *vals, int count)
|
||||||
#endif
|
#endif
|
||||||
{
|
{
|
||||||
CPUARMState *env = (CPUARMState *)ctx->data;
|
CPUARMState *env = (CPUARMState *)ctx->data;
|
||||||
|
@ -434,7 +445,7 @@ int arm_context_reg_write(struct uc_context *ctx, unsigned int *regs, void* cons
|
||||||
|
|
||||||
static bool arm_stop_interrupt(struct uc_struct *uc, int intno)
|
static bool arm_stop_interrupt(struct uc_struct *uc, int intno)
|
||||||
{
|
{
|
||||||
switch(intno) {
|
switch (intno) {
|
||||||
default:
|
default:
|
||||||
return false;
|
return false;
|
||||||
case EXCP_UDEF:
|
case EXCP_UDEF:
|
||||||
|
@ -446,17 +457,19 @@ static bool arm_stop_interrupt(struct uc_struct *uc, int intno)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
static uc_err arm_query(struct uc_struct *uc, uc_query_type type, size_t *result)
|
static uc_err arm_query(struct uc_struct *uc, uc_query_type type,
|
||||||
|
size_t *result)
|
||||||
{
|
{
|
||||||
CPUState *mycpu = uc->cpu;
|
CPUState *mycpu = uc->cpu;
|
||||||
uint32_t mode;
|
uint32_t mode;
|
||||||
|
|
||||||
switch(type) {
|
switch (type) {
|
||||||
case UC_QUERY_MODE:
|
case UC_QUERY_MODE:
|
||||||
// zero out ARM/THUMB mode
|
// zero out ARM/THUMB mode
|
||||||
mode = uc->mode & ~(UC_MODE_ARM | UC_MODE_THUMB);
|
mode = uc->mode & ~(UC_MODE_ARM | UC_MODE_THUMB);
|
||||||
// THUMB mode or ARM MOde
|
// THUMB mode or ARM MOde
|
||||||
mode += ((ARM_CPU(mycpu)->env.thumb != 0)? UC_MODE_THUMB : UC_MODE_ARM);
|
mode +=
|
||||||
|
((ARM_CPU(mycpu)->env.thumb != 0) ? UC_MODE_THUMB : UC_MODE_ARM);
|
||||||
*result = mode;
|
*result = mode;
|
||||||
return UC_ERR_OK;
|
return UC_ERR_OK;
|
||||||
default:
|
default:
|
||||||
|
@ -477,9 +490,9 @@ static int arm_cpus_init(struct uc_struct *uc, const char *cpu_model)
|
||||||
}
|
}
|
||||||
|
|
||||||
#ifdef TARGET_WORDS_BIGENDIAN
|
#ifdef TARGET_WORDS_BIGENDIAN
|
||||||
void armeb_uc_init(struct uc_struct* uc)
|
void armeb_uc_init(struct uc_struct *uc)
|
||||||
#else
|
#else
|
||||||
void arm_uc_init(struct uc_struct* uc)
|
void arm_uc_init(struct uc_struct *uc)
|
||||||
#endif
|
#endif
|
||||||
{
|
{
|
||||||
uc->reg_read = arm_reg_read;
|
uc->reg_read = arm_reg_read;
|
||||||
|
|
Loading…
Reference in New Issue