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changed the constants in the newest regression and sample files

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mothran 2015-08-23 21:51:53 -07:00
parent 995924176a
commit 1dd3334f87
3 changed files with 7 additions and 7 deletions
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4
bindings/python/sample_arm.py
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@ -76,7 +76,7 @@ def test_thumb():
mu.mem_write(ADDRESS, THUMB_CODE) mu.mem_write(ADDRESS, THUMB_CODE)
# initialize machine registers # initialize machine registers
mu.reg_write(ARM_REG_SP, 0x1234) mu.reg_write(UC_ARM_REG_SP, 0x1234)
# tracing all basic blocks with customized callback # tracing all basic blocks with customized callback
mu.hook_add(UC_HOOK_BLOCK, hook_block) mu.hook_add(UC_HOOK_BLOCK, hook_block)
@ -90,7 +90,7 @@ def test_thumb():
# now print out some registers # now print out some registers
print(">>> Emulation done. Below is the CPU context") print(">>> Emulation done. Below is the CPU context")
sp = mu.reg_read(ARM_REG_SP) sp = mu.reg_read(UC_ARM_REG_SP)
print(">>> SP = 0x%x" %sp) print(">>> SP = 0x%x" %sp)
except UcError as e: except UcError as e:

2
regress/callback-pc.py
View File

@ -38,7 +38,7 @@ def instruction_trace_test():
mu.mem_write(BASE_ADDRESS, THUMB_CODE) mu.mem_write(BASE_ADDRESS, THUMB_CODE)
# setup stack # setup stack
mu.reg_write(ARM_REG_SP, BASE_ADDRESS + 2 * 1024 * 1024) mu.reg_write(UC_ARM_REG_SP, BASE_ADDRESS + 2 * 1024 * 1024)
# tracing all instructions with customized callback # tracing all instructions with customized callback
mu.hook_add(UC_HOOK_CODE, hook_code, user_data=mu) mu.hook_add(UC_HOOK_CODE, hook_code, user_data=mu)

8
regress/wrong_sp_arm.py
View File

@ -6,17 +6,17 @@ from unicorn.arm_const import *
try: try:
uc = Uc(UC_ARCH_ARM, UC_MODE_32) uc = Uc(UC_ARCH_ARM, UC_MODE_32)
uc.reg_write(ARM_REG_SP, 4) uc.reg_write(UC_ARM_REG_SP, 4)
print 'Writing 4 to SP' print 'Writing 4 to SP'
print 'SP =', uc.reg_read(ARM_REG_SP) print 'SP =', uc.reg_read(UC_ARM_REG_SP)
except UcError as e: except UcError as e:
print("ERROR: %s" % e) print("ERROR: %s" % e)
try: try:
print "===========" print "==========="
uc = Uc(UC_ARCH_ARM, UC_MODE_ARM) uc = Uc(UC_ARCH_ARM, UC_MODE_ARM)
uc.reg_write(ARM_REG_SP, 4) uc.reg_write(UC_ARM_REG_SP, 4)
print 'Writing 4 to SP' print 'Writing 4 to SP'
print 'SP =', uc.reg_read(ARM_REG_SP) print 'SP =', uc.reg_read(UC_ARM_REG_SP)
except UcError as e: except UcError as e:
print("ERROR: %s" % e) print("ERROR: %s" % e)