From 1dd3334f871333f15e02d1fa7459ab00d11335b5 Mon Sep 17 00:00:00 2001 From: mothran Date: Sun, 23 Aug 2015 21:51:53 -0700 Subject: [PATCH] changed the constants in the newest regression and sample files --- bindings/python/sample_arm.py | 4 ++-- regress/callback-pc.py | 2 +- regress/wrong_sp_arm.py | 8 ++++---- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/bindings/python/sample_arm.py b/bindings/python/sample_arm.py index 4d7586d4..671b66b8 100755 --- a/bindings/python/sample_arm.py +++ b/bindings/python/sample_arm.py @@ -76,7 +76,7 @@ def test_thumb(): mu.mem_write(ADDRESS, THUMB_CODE) # initialize machine registers - mu.reg_write(ARM_REG_SP, 0x1234) + mu.reg_write(UC_ARM_REG_SP, 0x1234) # tracing all basic blocks with customized callback mu.hook_add(UC_HOOK_BLOCK, hook_block) @@ -90,7 +90,7 @@ def test_thumb(): # now print out some registers print(">>> Emulation done. Below is the CPU context") - sp = mu.reg_read(ARM_REG_SP) + sp = mu.reg_read(UC_ARM_REG_SP) print(">>> SP = 0x%x" %sp) except UcError as e: diff --git a/regress/callback-pc.py b/regress/callback-pc.py index aa6ff59e..be35a244 100755 --- a/regress/callback-pc.py +++ b/regress/callback-pc.py @@ -38,7 +38,7 @@ def instruction_trace_test(): mu.mem_write(BASE_ADDRESS, THUMB_CODE) # setup stack - mu.reg_write(ARM_REG_SP, BASE_ADDRESS + 2 * 1024 * 1024) + mu.reg_write(UC_ARM_REG_SP, BASE_ADDRESS + 2 * 1024 * 1024) # tracing all instructions with customized callback mu.hook_add(UC_HOOK_CODE, hook_code, user_data=mu) diff --git a/regress/wrong_sp_arm.py b/regress/wrong_sp_arm.py index 9886192a..762210f3 100755 --- a/regress/wrong_sp_arm.py +++ b/regress/wrong_sp_arm.py @@ -6,17 +6,17 @@ from unicorn.arm_const import * try: uc = Uc(UC_ARCH_ARM, UC_MODE_32) - uc.reg_write(ARM_REG_SP, 4) + uc.reg_write(UC_ARM_REG_SP, 4) print 'Writing 4 to SP' - print 'SP =', uc.reg_read(ARM_REG_SP) + print 'SP =', uc.reg_read(UC_ARM_REG_SP) except UcError as e: print("ERROR: %s" % e) try: print "===========" uc = Uc(UC_ARCH_ARM, UC_MODE_ARM) - uc.reg_write(ARM_REG_SP, 4) + uc.reg_write(UC_ARM_REG_SP, 4) print 'Writing 4 to SP' - print 'SP =', uc.reg_read(ARM_REG_SP) + print 'SP =', uc.reg_read(UC_ARM_REG_SP) except UcError as e: print("ERROR: %s" % e)