ad75a51e84
Allow the name 'cpu_env' to be used for something else. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
106 lines
2.8 KiB
C++
106 lines
2.8 KiB
C++
/*
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* Power ISA decode for Storage Control instructions
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*
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* Copyright (c) 2022 Instituto de Pesquisas Eldorado (eldorado.org.br)
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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* Processor Control Instructions
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*/
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static bool trans_MSGCLR(DisasContext *ctx, arg_X_rb *a)
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{
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if (!(ctx->insns_flags2 & PPC2_ISA207S)) {
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/*
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* Before Power ISA 2.07, processor control instructions were only
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* implemented in the "Embedded.Processor Control" category.
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*/
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REQUIRE_INSNS_FLAGS2(ctx, PRCNTL);
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}
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REQUIRE_HV(ctx);
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#if !defined(CONFIG_USER_ONLY)
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if (is_book3s_arch2x(ctx)) {
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gen_helper_book3s_msgclr(tcg_env, cpu_gpr[a->rb]);
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} else {
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gen_helper_msgclr(tcg_env, cpu_gpr[a->rb]);
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}
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#else
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qemu_build_not_reached();
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#endif
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return true;
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}
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static bool trans_MSGSND(DisasContext *ctx, arg_X_rb *a)
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{
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if (!(ctx->insns_flags2 & PPC2_ISA207S)) {
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/*
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* Before Power ISA 2.07, processor control instructions were only
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* implemented in the "Embedded.Processor Control" category.
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*/
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REQUIRE_INSNS_FLAGS2(ctx, PRCNTL);
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}
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REQUIRE_HV(ctx);
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#if !defined(CONFIG_USER_ONLY)
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if (is_book3s_arch2x(ctx)) {
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gen_helper_book3s_msgsnd(cpu_gpr[a->rb]);
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} else {
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gen_helper_msgsnd(cpu_gpr[a->rb]);
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}
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#else
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qemu_build_not_reached();
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#endif
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return true;
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}
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static bool trans_MSGCLRP(DisasContext *ctx, arg_X_rb *a)
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{
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REQUIRE_64BIT(ctx);
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REQUIRE_INSNS_FLAGS2(ctx, ISA207S);
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REQUIRE_SV(ctx);
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#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
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gen_helper_book3s_msgclrp(tcg_env, cpu_gpr[a->rb]);
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#else
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qemu_build_not_reached();
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#endif
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return true;
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}
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static bool trans_MSGSNDP(DisasContext *ctx, arg_X_rb *a)
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{
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REQUIRE_64BIT(ctx);
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REQUIRE_INSNS_FLAGS2(ctx, ISA207S);
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REQUIRE_SV(ctx);
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#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
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gen_helper_book3s_msgsndp(tcg_env, cpu_gpr[a->rb]);
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#else
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qemu_build_not_reached();
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#endif
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return true;
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}
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static bool trans_MSGSYNC(DisasContext *ctx, arg_MSGSYNC *a)
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{
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REQUIRE_INSNS_FLAGS2(ctx, ISA300);
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REQUIRE_HV(ctx);
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/* interpreted as no-op */
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return true;
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}
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