qemu/target/riscv/insn_trans
Tony Nguyen 14776ab5a1 tcg: TCGMemOp is now accelerator independent MemOp
Preparation for collapsing the two byte swaps, adjust_endianness and
handle_bswap, along the I/O path.

Target dependant attributes are conditionalized upon NEED_CPU_H.

Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Cornelia Huck <cohuck@redhat.com>
Message-Id: <81d9cd7d7f5aaadfa772d6c48ecee834e9cf7882.1566466906.git.tony.nguyen@bt.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-09-03 08:30:38 -07:00
..
trans_privileged.inc.c target/riscv: Add the privledge spec version 1.11.0 2019-06-24 01:03:45 -07:00
trans_rva.inc.c tcg: TCGMemOp is now accelerator independent MemOp 2019-09-03 08:30:38 -07:00
trans_rvd.inc.c target/riscv: Convert RV64D insns to decodetree 2019-03-13 10:34:06 +01:00
trans_rvf.inc.c target/riscv: Convert RV64F insns to decodetree 2019-03-13 10:34:06 +01:00
trans_rvi.inc.c tcg: TCGMemOp is now accelerator independent MemOp 2019-09-03 08:30:38 -07:00
trans_rvm.inc.c target/riscv: Zero extend the inputs of divuw and remuw 2019-03-22 00:26:39 -07:00