qemu/target
Richard Henderson fe636d3722 target/openrisc: Check CPUCFG_OF32S for float insns
Make sure the OF32S insns are enabled before allowing execution.
Include the missing bit for cpu "any".

Reviewed-by: Stafford Horne <shorne@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-09-04 12:53:10 -07:00
..
alpha tcg: TCGMemOp is now accelerator independent MemOp 2019-09-03 08:30:38 -07:00
arm Allow page table bit to swap endianness. 2019-09-04 16:29:18 +01:00
cris
hppa hppa/tcg: Call probe_write() also for CONFIG_USER_ONLY 2019-09-03 08:34:18 -07:00
i386 tcg: TCGMemOp is now accelerator independent MemOp 2019-09-03 08:30:38 -07:00
lm32
m68k tcg: TCGMemOp is now accelerator independent MemOp 2019-09-03 08:30:38 -07:00
microblaze tcg: TCGMemOp is now accelerator independent MemOp 2019-09-03 08:30:38 -07:00
mips Allow page table bit to swap endianness. 2019-09-04 16:29:18 +01:00
moxie
nios2
openrisc target/openrisc: Check CPUCFG_OF32S for float insns 2019-09-04 12:53:10 -07:00
ppc Allow page table bit to swap endianness. 2019-09-04 16:29:18 +01:00
riscv tcg: TCGMemOp is now accelerator independent MemOp 2019-09-03 08:30:38 -07:00
s390x s390x/tcg: Pass a size to probe_write() in do_csst() 2019-09-03 08:34:18 -07:00
sh4
sparc target/sparc: sun4u Invert Endian TTE bit 2019-09-03 08:30:39 -07:00
tilegx tcg: TCGMemOp is now accelerator independent MemOp 2019-09-03 08:30:38 -07:00
tricore tcg: TCGMemOp is now accelerator independent MemOp 2019-09-03 08:30:38 -07:00
unicore32
xtensa