qemu/target
Peter Maydell f6287c24c6 target/arm: Correctly implement ACTLR2, HACTLR2
The ACTLR2 and HACTLR2 AArch32 system registers didn't exist in ARMv7
or the original ARMv8.  They were later added as optional registers,
whose presence is signaled by the ID_MMFR4.AC2 field.  From ARMv8.2
they are mandatory (ie ID_MMFR4.AC2 must be non-zero).

We implemented HACTLR2 in commit 0e0456ab88, but we
incorrectly made it exist for all v8 CPUs, and we didn't implement
ACTLR2 at all.

Sort this out by implementing both registers only when they are
supposed to exist, and setting the ID_MMFR4 bit for -cpu max.

Note that this removes HACTLR2 from our Cortex-A53, -A47 and -A72
CPU models; this is correct, because those CPUs do not implement
this register.

Fixes: 0e0456ab88
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200214175116.9164-22-peter.maydell@linaro.org
2020-02-21 16:07:02 +00:00
..
alpha tcg: Search includes from the project root source directory 2020-01-15 15:13:10 -10:00
arm target/arm: Correctly implement ACTLR2, HACTLR2 2020-02-21 16:07:02 +00:00
cris cpu: Use cpu_class_set_parent_reset() 2020-01-24 20:59:06 +01:00
hppa target/hppa: Allow, but diagnose, LDCW aligned only mod 4 2020-01-27 10:49:51 -08:00
i386 target/i386/whpx: Remove superfluous semicolon 2020-02-18 20:20:49 +01:00
lm32 cpu: Use cpu_class_set_parent_reset() 2020-01-24 20:59:06 +01:00
m68k cpu: Use cpu_class_set_parent_reset() 2020-01-24 20:59:06 +01:00
microblaze qdev: set properties with device_class_set_props() 2020-01-24 20:59:15 +01:00
mips target/mips: Separate FPU-related helpers into their own file 2020-02-04 08:53:54 +01:00
moxie cpu: Use cpu_class_set_parent_reset() 2020-01-24 20:59:06 +01:00
nios2 qdev: set properties with device_class_set_props() 2020-01-24 20:59:15 +01:00
openrisc cpu: Use cpu_class_set_parent_reset() 2020-01-24 20:59:06 +01:00
ppc target/ppc/cpu.h: Clean up comments in the struct CPUPPCState definition 2020-02-21 09:15:04 +11:00
riscv riscv: Separate FPU register size from core register size in gdbstub [v2] 2020-02-10 12:01:36 -08:00
s390x s390x: sigp: Fix sense running reporting 2020-01-27 12:13:10 +01:00
sh4 cpu: Use cpu_class_set_parent_reset() 2020-01-24 20:59:06 +01:00
sparc qdev: set properties with device_class_set_props() 2020-01-24 20:59:15 +01:00
tilegx cpu: Use cpu_class_set_parent_reset() 2020-01-24 20:59:06 +01:00
tricore cpu: Use cpu_class_set_parent_reset() 2020-01-24 20:59:06 +01:00
unicore32 tcg: Search includes from the project root source directory 2020-01-15 15:13:10 -10:00
xtensa cpu: Use cpu_class_set_parent_reset() 2020-01-24 20:59:06 +01:00