qemu/hw/riscv
Eduardo Habkost fabbcbd953 sifive_e: Register "revb" as class property
Class properties make QOM introspection simpler and easier, as
they don't require an object to be instantiated.

Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20200921221045.699690-24-ehabkost@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2020-09-22 16:48:29 -04:00
..
boot.c RISC-V: Support 64 bit start address 2020-07-13 17:25:37 -07:00
Kconfig hw/riscv: Sort the Kconfig options in alphabetical order 2020-09-09 15:54:19 -07:00
meson.build hw/riscv: Always build riscv_hart.c 2020-09-09 15:54:19 -07:00
microchip_pfsoc.c hw/riscv: Move sifive_plic model to hw/intc 2020-09-09 15:54:19 -07:00
numa.c hw/riscv: Add helpers for RISC-V multi-socket NUMA machines 2020-08-25 09:11:35 -07:00
opentitan.c target/riscv: cpu: Set reset vector based on the configured property value 2020-09-09 15:54:18 -07:00
riscv_hart.c hw/riscv: hart: Add a new 'resetvec' property 2020-09-09 15:54:18 -07:00
sifive_e.c sifive_e: Register "revb" as class property 2020-09-22 16:48:29 -04:00
sifive_u.c sifive_u: Rename memmap enum constants 2020-09-18 13:49:48 -04:00
spike.c hw/riscv: Move riscv_htif model to hw/char 2020-09-09 15:54:19 -07:00
virt.c hw/riscv: Move sifive_test model to hw/misc 2020-09-09 15:54:19 -07:00