f8c45c6550
This speeds up SMM switches. Later on it may remove the need to take the BQL, and it may also allow to reuse code between TCG and KVM. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
922 lines
27 KiB
C
922 lines
27 KiB
C
#include "qemu/osdep.h"
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#include "qemu-common.h"
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#include "cpu.h"
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#include "exec/exec-all.h"
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#include "hw/hw.h"
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#include "hw/boards.h"
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#include "hw/i386/pc.h"
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#include "hw/isa/isa.h"
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#include "migration/cpu.h"
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#include "sysemu/kvm.h"
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#include "qemu/error-report.h"
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static const VMStateDescription vmstate_segment = {
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.name = "segment",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(selector, SegmentCache),
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VMSTATE_UINTTL(base, SegmentCache),
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VMSTATE_UINT32(limit, SegmentCache),
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VMSTATE_UINT32(flags, SegmentCache),
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VMSTATE_END_OF_LIST()
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}
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};
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#define VMSTATE_SEGMENT(_field, _state) { \
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.name = (stringify(_field)), \
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.size = sizeof(SegmentCache), \
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.vmsd = &vmstate_segment, \
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.flags = VMS_STRUCT, \
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.offset = offsetof(_state, _field) \
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+ type_check(SegmentCache,typeof_field(_state, _field)) \
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}
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#define VMSTATE_SEGMENT_ARRAY(_field, _state, _n) \
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VMSTATE_STRUCT_ARRAY(_field, _state, _n, 0, vmstate_segment, SegmentCache)
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static const VMStateDescription vmstate_xmm_reg = {
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.name = "xmm_reg",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT64(ZMM_Q(0), ZMMReg),
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VMSTATE_UINT64(ZMM_Q(1), ZMMReg),
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VMSTATE_END_OF_LIST()
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}
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};
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#define VMSTATE_XMM_REGS(_field, _state, _start) \
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VMSTATE_STRUCT_SUB_ARRAY(_field, _state, _start, CPU_NB_REGS, 0, \
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vmstate_xmm_reg, ZMMReg)
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/* YMMH format is the same as XMM, but for bits 128-255 */
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static const VMStateDescription vmstate_ymmh_reg = {
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.name = "ymmh_reg",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT64(ZMM_Q(2), ZMMReg),
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VMSTATE_UINT64(ZMM_Q(3), ZMMReg),
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VMSTATE_END_OF_LIST()
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}
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};
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#define VMSTATE_YMMH_REGS_VARS(_field, _state, _start, _v) \
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VMSTATE_STRUCT_SUB_ARRAY(_field, _state, _start, CPU_NB_REGS, _v, \
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vmstate_ymmh_reg, ZMMReg)
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static const VMStateDescription vmstate_zmmh_reg = {
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.name = "zmmh_reg",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT64(ZMM_Q(4), ZMMReg),
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VMSTATE_UINT64(ZMM_Q(5), ZMMReg),
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VMSTATE_UINT64(ZMM_Q(6), ZMMReg),
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VMSTATE_UINT64(ZMM_Q(7), ZMMReg),
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VMSTATE_END_OF_LIST()
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}
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};
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#define VMSTATE_ZMMH_REGS_VARS(_field, _state, _start) \
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VMSTATE_STRUCT_SUB_ARRAY(_field, _state, _start, CPU_NB_REGS, 0, \
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vmstate_zmmh_reg, ZMMReg)
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#ifdef TARGET_X86_64
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static const VMStateDescription vmstate_hi16_zmm_reg = {
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.name = "hi16_zmm_reg",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT64(ZMM_Q(0), ZMMReg),
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VMSTATE_UINT64(ZMM_Q(1), ZMMReg),
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VMSTATE_UINT64(ZMM_Q(2), ZMMReg),
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VMSTATE_UINT64(ZMM_Q(3), ZMMReg),
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VMSTATE_UINT64(ZMM_Q(4), ZMMReg),
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VMSTATE_UINT64(ZMM_Q(5), ZMMReg),
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VMSTATE_UINT64(ZMM_Q(6), ZMMReg),
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VMSTATE_UINT64(ZMM_Q(7), ZMMReg),
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VMSTATE_END_OF_LIST()
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}
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};
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#define VMSTATE_Hi16_ZMM_REGS_VARS(_field, _state, _start) \
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VMSTATE_STRUCT_SUB_ARRAY(_field, _state, _start, CPU_NB_REGS, 0, \
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vmstate_hi16_zmm_reg, ZMMReg)
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#endif
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static const VMStateDescription vmstate_bnd_regs = {
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.name = "bnd_regs",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT64(lb, BNDReg),
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VMSTATE_UINT64(ub, BNDReg),
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VMSTATE_END_OF_LIST()
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}
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};
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#define VMSTATE_BND_REGS(_field, _state, _n) \
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VMSTATE_STRUCT_ARRAY(_field, _state, _n, 0, vmstate_bnd_regs, BNDReg)
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static const VMStateDescription vmstate_mtrr_var = {
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.name = "mtrr_var",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT64(base, MTRRVar),
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VMSTATE_UINT64(mask, MTRRVar),
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VMSTATE_END_OF_LIST()
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}
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};
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#define VMSTATE_MTRR_VARS(_field, _state, _n, _v) \
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VMSTATE_STRUCT_ARRAY(_field, _state, _n, _v, vmstate_mtrr_var, MTRRVar)
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typedef struct x86_FPReg_tmp {
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FPReg *parent;
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uint64_t tmp_mant;
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uint16_t tmp_exp;
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} x86_FPReg_tmp;
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static void fpreg_pre_save(void *opaque)
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{
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x86_FPReg_tmp *tmp = opaque;
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/* we save the real CPU data (in case of MMX usage only 'mant'
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contains the MMX register */
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cpu_get_fp80(&tmp->tmp_mant, &tmp->tmp_exp, tmp->parent->d);
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}
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static int fpreg_post_load(void *opaque, int version)
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{
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x86_FPReg_tmp *tmp = opaque;
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tmp->parent->d = cpu_set_fp80(tmp->tmp_mant, tmp->tmp_exp);
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return 0;
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}
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static const VMStateDescription vmstate_fpreg_tmp = {
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.name = "fpreg_tmp",
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.post_load = fpreg_post_load,
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.pre_save = fpreg_pre_save,
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.fields = (VMStateField[]) {
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VMSTATE_UINT64(tmp_mant, x86_FPReg_tmp),
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VMSTATE_UINT16(tmp_exp, x86_FPReg_tmp),
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VMSTATE_END_OF_LIST()
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}
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};
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static const VMStateDescription vmstate_fpreg = {
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.name = "fpreg",
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.fields = (VMStateField[]) {
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VMSTATE_WITH_TMP(FPReg, x86_FPReg_tmp, vmstate_fpreg_tmp),
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VMSTATE_END_OF_LIST()
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}
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};
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static void cpu_pre_save(void *opaque)
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{
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X86CPU *cpu = opaque;
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CPUX86State *env = &cpu->env;
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int i;
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/* FPU */
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env->fpus_vmstate = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
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env->fptag_vmstate = 0;
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for(i = 0; i < 8; i++) {
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env->fptag_vmstate |= ((!env->fptags[i]) << i);
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}
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env->fpregs_format_vmstate = 0;
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/*
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* Real mode guest segments register DPL should be zero.
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* Older KVM version were setting it wrongly.
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* Fixing it will allow live migration to host with unrestricted guest
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* support (otherwise the migration will fail with invalid guest state
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* error).
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*/
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if (!(env->cr[0] & CR0_PE_MASK) &&
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(env->segs[R_CS].flags >> DESC_DPL_SHIFT & 3) != 0) {
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env->segs[R_CS].flags &= ~(env->segs[R_CS].flags & DESC_DPL_MASK);
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env->segs[R_DS].flags &= ~(env->segs[R_DS].flags & DESC_DPL_MASK);
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env->segs[R_ES].flags &= ~(env->segs[R_ES].flags & DESC_DPL_MASK);
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env->segs[R_FS].flags &= ~(env->segs[R_FS].flags & DESC_DPL_MASK);
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env->segs[R_GS].flags &= ~(env->segs[R_GS].flags & DESC_DPL_MASK);
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env->segs[R_SS].flags &= ~(env->segs[R_SS].flags & DESC_DPL_MASK);
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}
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}
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static int cpu_post_load(void *opaque, int version_id)
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{
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X86CPU *cpu = opaque;
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CPUState *cs = CPU(cpu);
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CPUX86State *env = &cpu->env;
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int i;
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if (env->tsc_khz && env->user_tsc_khz &&
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env->tsc_khz != env->user_tsc_khz) {
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error_report("Mismatch between user-specified TSC frequency and "
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"migrated TSC frequency");
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return -EINVAL;
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}
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if (env->fpregs_format_vmstate) {
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error_report("Unsupported old non-softfloat CPU state");
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return -EINVAL;
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}
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/*
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* Real mode guest segments register DPL should be zero.
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* Older KVM version were setting it wrongly.
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* Fixing it will allow live migration from such host that don't have
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* restricted guest support to a host with unrestricted guest support
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* (otherwise the migration will fail with invalid guest state
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* error).
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*/
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if (!(env->cr[0] & CR0_PE_MASK) &&
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(env->segs[R_CS].flags >> DESC_DPL_SHIFT & 3) != 0) {
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env->segs[R_CS].flags &= ~(env->segs[R_CS].flags & DESC_DPL_MASK);
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env->segs[R_DS].flags &= ~(env->segs[R_DS].flags & DESC_DPL_MASK);
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env->segs[R_ES].flags &= ~(env->segs[R_ES].flags & DESC_DPL_MASK);
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env->segs[R_FS].flags &= ~(env->segs[R_FS].flags & DESC_DPL_MASK);
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env->segs[R_GS].flags &= ~(env->segs[R_GS].flags & DESC_DPL_MASK);
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env->segs[R_SS].flags &= ~(env->segs[R_SS].flags & DESC_DPL_MASK);
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}
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/* Older versions of QEMU incorrectly used CS.DPL as the CPL when
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* running under KVM. This is wrong for conforming code segments.
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* Luckily, in our implementation the CPL field of hflags is redundant
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* and we can get the right value from the SS descriptor privilege level.
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*/
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env->hflags &= ~HF_CPL_MASK;
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env->hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
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env->fpstt = (env->fpus_vmstate >> 11) & 7;
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env->fpus = env->fpus_vmstate & ~0x3800;
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env->fptag_vmstate ^= 0xff;
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for(i = 0; i < 8; i++) {
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env->fptags[i] = (env->fptag_vmstate >> i) & 1;
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}
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update_fp_status(env);
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cpu_breakpoint_remove_all(cs, BP_CPU);
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cpu_watchpoint_remove_all(cs, BP_CPU);
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{
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/* Indicate all breakpoints disabled, as they are, then
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let the helper re-enable them. */
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target_ulong dr7 = env->dr[7];
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env->dr[7] = dr7 & ~(DR7_GLOBAL_BP_MASK | DR7_LOCAL_BP_MASK);
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cpu_x86_update_dr7(env, dr7);
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}
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tlb_flush(cs);
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return 0;
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}
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static bool async_pf_msr_needed(void *opaque)
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{
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X86CPU *cpu = opaque;
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return cpu->env.async_pf_en_msr != 0;
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}
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static bool pv_eoi_msr_needed(void *opaque)
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{
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X86CPU *cpu = opaque;
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return cpu->env.pv_eoi_en_msr != 0;
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}
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static bool steal_time_msr_needed(void *opaque)
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{
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X86CPU *cpu = opaque;
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return cpu->env.steal_time_msr != 0;
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}
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static const VMStateDescription vmstate_steal_time_msr = {
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.name = "cpu/steal_time_msr",
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.version_id = 1,
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.minimum_version_id = 1,
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.needed = steal_time_msr_needed,
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.fields = (VMStateField[]) {
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VMSTATE_UINT64(env.steal_time_msr, X86CPU),
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VMSTATE_END_OF_LIST()
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}
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};
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static const VMStateDescription vmstate_async_pf_msr = {
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.name = "cpu/async_pf_msr",
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.version_id = 1,
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.minimum_version_id = 1,
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.needed = async_pf_msr_needed,
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.fields = (VMStateField[]) {
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VMSTATE_UINT64(env.async_pf_en_msr, X86CPU),
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VMSTATE_END_OF_LIST()
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}
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};
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static const VMStateDescription vmstate_pv_eoi_msr = {
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.name = "cpu/async_pv_eoi_msr",
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.version_id = 1,
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.minimum_version_id = 1,
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.needed = pv_eoi_msr_needed,
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.fields = (VMStateField[]) {
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VMSTATE_UINT64(env.pv_eoi_en_msr, X86CPU),
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VMSTATE_END_OF_LIST()
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}
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};
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static bool fpop_ip_dp_needed(void *opaque)
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{
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X86CPU *cpu = opaque;
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CPUX86State *env = &cpu->env;
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return env->fpop != 0 || env->fpip != 0 || env->fpdp != 0;
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}
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static const VMStateDescription vmstate_fpop_ip_dp = {
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.name = "cpu/fpop_ip_dp",
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.version_id = 1,
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.minimum_version_id = 1,
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.needed = fpop_ip_dp_needed,
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.fields = (VMStateField[]) {
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VMSTATE_UINT16(env.fpop, X86CPU),
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VMSTATE_UINT64(env.fpip, X86CPU),
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VMSTATE_UINT64(env.fpdp, X86CPU),
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VMSTATE_END_OF_LIST()
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}
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};
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static bool tsc_adjust_needed(void *opaque)
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{
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X86CPU *cpu = opaque;
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CPUX86State *env = &cpu->env;
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return env->tsc_adjust != 0;
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}
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static const VMStateDescription vmstate_msr_tsc_adjust = {
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.name = "cpu/msr_tsc_adjust",
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.version_id = 1,
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.minimum_version_id = 1,
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.needed = tsc_adjust_needed,
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.fields = (VMStateField[]) {
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VMSTATE_UINT64(env.tsc_adjust, X86CPU),
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VMSTATE_END_OF_LIST()
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}
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};
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static bool tscdeadline_needed(void *opaque)
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{
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X86CPU *cpu = opaque;
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CPUX86State *env = &cpu->env;
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return env->tsc_deadline != 0;
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}
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static const VMStateDescription vmstate_msr_tscdeadline = {
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.name = "cpu/msr_tscdeadline",
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.version_id = 1,
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.minimum_version_id = 1,
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.needed = tscdeadline_needed,
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.fields = (VMStateField[]) {
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VMSTATE_UINT64(env.tsc_deadline, X86CPU),
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VMSTATE_END_OF_LIST()
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}
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};
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static bool misc_enable_needed(void *opaque)
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{
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X86CPU *cpu = opaque;
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CPUX86State *env = &cpu->env;
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return env->msr_ia32_misc_enable != MSR_IA32_MISC_ENABLE_DEFAULT;
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}
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static bool feature_control_needed(void *opaque)
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{
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X86CPU *cpu = opaque;
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CPUX86State *env = &cpu->env;
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return env->msr_ia32_feature_control != 0;
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}
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static const VMStateDescription vmstate_msr_ia32_misc_enable = {
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.name = "cpu/msr_ia32_misc_enable",
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.version_id = 1,
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.minimum_version_id = 1,
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.needed = misc_enable_needed,
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.fields = (VMStateField[]) {
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VMSTATE_UINT64(env.msr_ia32_misc_enable, X86CPU),
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VMSTATE_END_OF_LIST()
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}
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};
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static const VMStateDescription vmstate_msr_ia32_feature_control = {
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.name = "cpu/msr_ia32_feature_control",
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.version_id = 1,
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.minimum_version_id = 1,
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.needed = feature_control_needed,
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.fields = (VMStateField[]) {
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VMSTATE_UINT64(env.msr_ia32_feature_control, X86CPU),
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VMSTATE_END_OF_LIST()
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}
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};
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static bool pmu_enable_needed(void *opaque)
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{
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X86CPU *cpu = opaque;
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CPUX86State *env = &cpu->env;
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int i;
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if (env->msr_fixed_ctr_ctrl || env->msr_global_ctrl ||
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env->msr_global_status || env->msr_global_ovf_ctrl) {
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return true;
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}
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for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
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if (env->msr_fixed_counters[i]) {
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return true;
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}
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}
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for (i = 0; i < MAX_GP_COUNTERS; i++) {
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if (env->msr_gp_counters[i] || env->msr_gp_evtsel[i]) {
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return true;
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}
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}
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return false;
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}
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static const VMStateDescription vmstate_msr_architectural_pmu = {
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.name = "cpu/msr_architectural_pmu",
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.version_id = 1,
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.minimum_version_id = 1,
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.needed = pmu_enable_needed,
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.fields = (VMStateField[]) {
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VMSTATE_UINT64(env.msr_fixed_ctr_ctrl, X86CPU),
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VMSTATE_UINT64(env.msr_global_ctrl, X86CPU),
|
|
VMSTATE_UINT64(env.msr_global_status, X86CPU),
|
|
VMSTATE_UINT64(env.msr_global_ovf_ctrl, X86CPU),
|
|
VMSTATE_UINT64_ARRAY(env.msr_fixed_counters, X86CPU, MAX_FIXED_COUNTERS),
|
|
VMSTATE_UINT64_ARRAY(env.msr_gp_counters, X86CPU, MAX_GP_COUNTERS),
|
|
VMSTATE_UINT64_ARRAY(env.msr_gp_evtsel, X86CPU, MAX_GP_COUNTERS),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
static bool mpx_needed(void *opaque)
|
|
{
|
|
X86CPU *cpu = opaque;
|
|
CPUX86State *env = &cpu->env;
|
|
unsigned int i;
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
if (env->bnd_regs[i].lb || env->bnd_regs[i].ub) {
|
|
return true;
|
|
}
|
|
}
|
|
|
|
if (env->bndcs_regs.cfgu || env->bndcs_regs.sts) {
|
|
return true;
|
|
}
|
|
|
|
return !!env->msr_bndcfgs;
|
|
}
|
|
|
|
static const VMStateDescription vmstate_mpx = {
|
|
.name = "cpu/mpx",
|
|
.version_id = 1,
|
|
.minimum_version_id = 1,
|
|
.needed = mpx_needed,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_BND_REGS(env.bnd_regs, X86CPU, 4),
|
|
VMSTATE_UINT64(env.bndcs_regs.cfgu, X86CPU),
|
|
VMSTATE_UINT64(env.bndcs_regs.sts, X86CPU),
|
|
VMSTATE_UINT64(env.msr_bndcfgs, X86CPU),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
static bool hyperv_hypercall_enable_needed(void *opaque)
|
|
{
|
|
X86CPU *cpu = opaque;
|
|
CPUX86State *env = &cpu->env;
|
|
|
|
return env->msr_hv_hypercall != 0 || env->msr_hv_guest_os_id != 0;
|
|
}
|
|
|
|
static const VMStateDescription vmstate_msr_hypercall_hypercall = {
|
|
.name = "cpu/msr_hyperv_hypercall",
|
|
.version_id = 1,
|
|
.minimum_version_id = 1,
|
|
.needed = hyperv_hypercall_enable_needed,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_UINT64(env.msr_hv_guest_os_id, X86CPU),
|
|
VMSTATE_UINT64(env.msr_hv_hypercall, X86CPU),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
static bool hyperv_vapic_enable_needed(void *opaque)
|
|
{
|
|
X86CPU *cpu = opaque;
|
|
CPUX86State *env = &cpu->env;
|
|
|
|
return env->msr_hv_vapic != 0;
|
|
}
|
|
|
|
static const VMStateDescription vmstate_msr_hyperv_vapic = {
|
|
.name = "cpu/msr_hyperv_vapic",
|
|
.version_id = 1,
|
|
.minimum_version_id = 1,
|
|
.needed = hyperv_vapic_enable_needed,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_UINT64(env.msr_hv_vapic, X86CPU),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
static bool hyperv_time_enable_needed(void *opaque)
|
|
{
|
|
X86CPU *cpu = opaque;
|
|
CPUX86State *env = &cpu->env;
|
|
|
|
return env->msr_hv_tsc != 0;
|
|
}
|
|
|
|
static const VMStateDescription vmstate_msr_hyperv_time = {
|
|
.name = "cpu/msr_hyperv_time",
|
|
.version_id = 1,
|
|
.minimum_version_id = 1,
|
|
.needed = hyperv_time_enable_needed,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_UINT64(env.msr_hv_tsc, X86CPU),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
static bool hyperv_crash_enable_needed(void *opaque)
|
|
{
|
|
X86CPU *cpu = opaque;
|
|
CPUX86State *env = &cpu->env;
|
|
int i;
|
|
|
|
for (i = 0; i < HV_X64_MSR_CRASH_PARAMS; i++) {
|
|
if (env->msr_hv_crash_params[i]) {
|
|
return true;
|
|
}
|
|
}
|
|
return false;
|
|
}
|
|
|
|
static const VMStateDescription vmstate_msr_hyperv_crash = {
|
|
.name = "cpu/msr_hyperv_crash",
|
|
.version_id = 1,
|
|
.minimum_version_id = 1,
|
|
.needed = hyperv_crash_enable_needed,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_UINT64_ARRAY(env.msr_hv_crash_params,
|
|
X86CPU, HV_X64_MSR_CRASH_PARAMS),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
static bool hyperv_runtime_enable_needed(void *opaque)
|
|
{
|
|
X86CPU *cpu = opaque;
|
|
CPUX86State *env = &cpu->env;
|
|
|
|
if (!cpu->hyperv_runtime) {
|
|
return false;
|
|
}
|
|
|
|
return env->msr_hv_runtime != 0;
|
|
}
|
|
|
|
static const VMStateDescription vmstate_msr_hyperv_runtime = {
|
|
.name = "cpu/msr_hyperv_runtime",
|
|
.version_id = 1,
|
|
.minimum_version_id = 1,
|
|
.needed = hyperv_runtime_enable_needed,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_UINT64(env.msr_hv_runtime, X86CPU),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
static bool hyperv_synic_enable_needed(void *opaque)
|
|
{
|
|
X86CPU *cpu = opaque;
|
|
CPUX86State *env = &cpu->env;
|
|
int i;
|
|
|
|
if (env->msr_hv_synic_control != 0 ||
|
|
env->msr_hv_synic_evt_page != 0 ||
|
|
env->msr_hv_synic_msg_page != 0) {
|
|
return true;
|
|
}
|
|
|
|
for (i = 0; i < ARRAY_SIZE(env->msr_hv_synic_sint); i++) {
|
|
if (env->msr_hv_synic_sint[i] != 0) {
|
|
return true;
|
|
}
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
static const VMStateDescription vmstate_msr_hyperv_synic = {
|
|
.name = "cpu/msr_hyperv_synic",
|
|
.version_id = 1,
|
|
.minimum_version_id = 1,
|
|
.needed = hyperv_synic_enable_needed,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_UINT64(env.msr_hv_synic_control, X86CPU),
|
|
VMSTATE_UINT64(env.msr_hv_synic_evt_page, X86CPU),
|
|
VMSTATE_UINT64(env.msr_hv_synic_msg_page, X86CPU),
|
|
VMSTATE_UINT64_ARRAY(env.msr_hv_synic_sint, X86CPU,
|
|
HV_SYNIC_SINT_COUNT),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
static bool hyperv_stimer_enable_needed(void *opaque)
|
|
{
|
|
X86CPU *cpu = opaque;
|
|
CPUX86State *env = &cpu->env;
|
|
int i;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(env->msr_hv_stimer_config); i++) {
|
|
if (env->msr_hv_stimer_config[i] || env->msr_hv_stimer_count[i]) {
|
|
return true;
|
|
}
|
|
}
|
|
return false;
|
|
}
|
|
|
|
static const VMStateDescription vmstate_msr_hyperv_stimer = {
|
|
.name = "cpu/msr_hyperv_stimer",
|
|
.version_id = 1,
|
|
.minimum_version_id = 1,
|
|
.needed = hyperv_stimer_enable_needed,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_UINT64_ARRAY(env.msr_hv_stimer_config,
|
|
X86CPU, HV_SYNIC_STIMER_COUNT),
|
|
VMSTATE_UINT64_ARRAY(env.msr_hv_stimer_count,
|
|
X86CPU, HV_SYNIC_STIMER_COUNT),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
static bool avx512_needed(void *opaque)
|
|
{
|
|
X86CPU *cpu = opaque;
|
|
CPUX86State *env = &cpu->env;
|
|
unsigned int i;
|
|
|
|
for (i = 0; i < NB_OPMASK_REGS; i++) {
|
|
if (env->opmask_regs[i]) {
|
|
return true;
|
|
}
|
|
}
|
|
|
|
for (i = 0; i < CPU_NB_REGS; i++) {
|
|
#define ENV_XMM(reg, field) (env->xmm_regs[reg].ZMM_Q(field))
|
|
if (ENV_XMM(i, 4) || ENV_XMM(i, 6) ||
|
|
ENV_XMM(i, 5) || ENV_XMM(i, 7)) {
|
|
return true;
|
|
}
|
|
#ifdef TARGET_X86_64
|
|
if (ENV_XMM(i+16, 0) || ENV_XMM(i+16, 1) ||
|
|
ENV_XMM(i+16, 2) || ENV_XMM(i+16, 3) ||
|
|
ENV_XMM(i+16, 4) || ENV_XMM(i+16, 5) ||
|
|
ENV_XMM(i+16, 6) || ENV_XMM(i+16, 7)) {
|
|
return true;
|
|
}
|
|
#endif
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
static const VMStateDescription vmstate_avx512 = {
|
|
.name = "cpu/avx512",
|
|
.version_id = 1,
|
|
.minimum_version_id = 1,
|
|
.needed = avx512_needed,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_UINT64_ARRAY(env.opmask_regs, X86CPU, NB_OPMASK_REGS),
|
|
VMSTATE_ZMMH_REGS_VARS(env.xmm_regs, X86CPU, 0),
|
|
#ifdef TARGET_X86_64
|
|
VMSTATE_Hi16_ZMM_REGS_VARS(env.xmm_regs, X86CPU, 16),
|
|
#endif
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
static bool xss_needed(void *opaque)
|
|
{
|
|
X86CPU *cpu = opaque;
|
|
CPUX86State *env = &cpu->env;
|
|
|
|
return env->xss != 0;
|
|
}
|
|
|
|
static const VMStateDescription vmstate_xss = {
|
|
.name = "cpu/xss",
|
|
.version_id = 1,
|
|
.minimum_version_id = 1,
|
|
.needed = xss_needed,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_UINT64(env.xss, X86CPU),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
#ifdef TARGET_X86_64
|
|
static bool pkru_needed(void *opaque)
|
|
{
|
|
X86CPU *cpu = opaque;
|
|
CPUX86State *env = &cpu->env;
|
|
|
|
return env->pkru != 0;
|
|
}
|
|
|
|
static const VMStateDescription vmstate_pkru = {
|
|
.name = "cpu/pkru",
|
|
.version_id = 1,
|
|
.minimum_version_id = 1,
|
|
.needed = pkru_needed,
|
|
.fields = (VMStateField[]){
|
|
VMSTATE_UINT32(env.pkru, X86CPU),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
#endif
|
|
|
|
static bool tsc_khz_needed(void *opaque)
|
|
{
|
|
X86CPU *cpu = opaque;
|
|
CPUX86State *env = &cpu->env;
|
|
MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
|
|
PCMachineClass *pcmc = PC_MACHINE_CLASS(mc);
|
|
return env->tsc_khz && pcmc->save_tsc_khz;
|
|
}
|
|
|
|
static const VMStateDescription vmstate_tsc_khz = {
|
|
.name = "cpu/tsc_khz",
|
|
.version_id = 1,
|
|
.minimum_version_id = 1,
|
|
.needed = tsc_khz_needed,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_INT64(env.tsc_khz, X86CPU),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
static bool mcg_ext_ctl_needed(void *opaque)
|
|
{
|
|
X86CPU *cpu = opaque;
|
|
CPUX86State *env = &cpu->env;
|
|
return cpu->enable_lmce && env->mcg_ext_ctl;
|
|
}
|
|
|
|
static const VMStateDescription vmstate_mcg_ext_ctl = {
|
|
.name = "cpu/mcg_ext_ctl",
|
|
.version_id = 1,
|
|
.minimum_version_id = 1,
|
|
.needed = mcg_ext_ctl_needed,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_UINT64(env.mcg_ext_ctl, X86CPU),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
VMStateDescription vmstate_x86_cpu = {
|
|
.name = "cpu",
|
|
.version_id = 12,
|
|
.minimum_version_id = 11,
|
|
.pre_save = cpu_pre_save,
|
|
.post_load = cpu_post_load,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_UINTTL_ARRAY(env.regs, X86CPU, CPU_NB_REGS),
|
|
VMSTATE_UINTTL(env.eip, X86CPU),
|
|
VMSTATE_UINTTL(env.eflags, X86CPU),
|
|
VMSTATE_UINT32(env.hflags, X86CPU),
|
|
/* FPU */
|
|
VMSTATE_UINT16(env.fpuc, X86CPU),
|
|
VMSTATE_UINT16(env.fpus_vmstate, X86CPU),
|
|
VMSTATE_UINT16(env.fptag_vmstate, X86CPU),
|
|
VMSTATE_UINT16(env.fpregs_format_vmstate, X86CPU),
|
|
|
|
VMSTATE_STRUCT_ARRAY(env.fpregs, X86CPU, 8, 0, vmstate_fpreg, FPReg),
|
|
|
|
VMSTATE_SEGMENT_ARRAY(env.segs, X86CPU, 6),
|
|
VMSTATE_SEGMENT(env.ldt, X86CPU),
|
|
VMSTATE_SEGMENT(env.tr, X86CPU),
|
|
VMSTATE_SEGMENT(env.gdt, X86CPU),
|
|
VMSTATE_SEGMENT(env.idt, X86CPU),
|
|
|
|
VMSTATE_UINT32(env.sysenter_cs, X86CPU),
|
|
VMSTATE_UINTTL(env.sysenter_esp, X86CPU),
|
|
VMSTATE_UINTTL(env.sysenter_eip, X86CPU),
|
|
|
|
VMSTATE_UINTTL(env.cr[0], X86CPU),
|
|
VMSTATE_UINTTL(env.cr[2], X86CPU),
|
|
VMSTATE_UINTTL(env.cr[3], X86CPU),
|
|
VMSTATE_UINTTL(env.cr[4], X86CPU),
|
|
VMSTATE_UINTTL_ARRAY(env.dr, X86CPU, 8),
|
|
/* MMU */
|
|
VMSTATE_INT32(env.a20_mask, X86CPU),
|
|
/* XMM */
|
|
VMSTATE_UINT32(env.mxcsr, X86CPU),
|
|
VMSTATE_XMM_REGS(env.xmm_regs, X86CPU, 0),
|
|
|
|
#ifdef TARGET_X86_64
|
|
VMSTATE_UINT64(env.efer, X86CPU),
|
|
VMSTATE_UINT64(env.star, X86CPU),
|
|
VMSTATE_UINT64(env.lstar, X86CPU),
|
|
VMSTATE_UINT64(env.cstar, X86CPU),
|
|
VMSTATE_UINT64(env.fmask, X86CPU),
|
|
VMSTATE_UINT64(env.kernelgsbase, X86CPU),
|
|
#endif
|
|
VMSTATE_UINT32(env.smbase, X86CPU),
|
|
|
|
VMSTATE_UINT64(env.pat, X86CPU),
|
|
VMSTATE_UINT32(env.hflags2, X86CPU),
|
|
|
|
VMSTATE_UINT64(env.vm_hsave, X86CPU),
|
|
VMSTATE_UINT64(env.vm_vmcb, X86CPU),
|
|
VMSTATE_UINT64(env.tsc_offset, X86CPU),
|
|
VMSTATE_UINT64(env.intercept, X86CPU),
|
|
VMSTATE_UINT16(env.intercept_cr_read, X86CPU),
|
|
VMSTATE_UINT16(env.intercept_cr_write, X86CPU),
|
|
VMSTATE_UINT16(env.intercept_dr_read, X86CPU),
|
|
VMSTATE_UINT16(env.intercept_dr_write, X86CPU),
|
|
VMSTATE_UINT32(env.intercept_exceptions, X86CPU),
|
|
VMSTATE_UINT8(env.v_tpr, X86CPU),
|
|
/* MTRRs */
|
|
VMSTATE_UINT64_ARRAY(env.mtrr_fixed, X86CPU, 11),
|
|
VMSTATE_UINT64(env.mtrr_deftype, X86CPU),
|
|
VMSTATE_MTRR_VARS(env.mtrr_var, X86CPU, MSR_MTRRcap_VCNT, 8),
|
|
/* KVM-related states */
|
|
VMSTATE_INT32(env.interrupt_injected, X86CPU),
|
|
VMSTATE_UINT32(env.mp_state, X86CPU),
|
|
VMSTATE_UINT64(env.tsc, X86CPU),
|
|
VMSTATE_INT32(env.exception_injected, X86CPU),
|
|
VMSTATE_UINT8(env.soft_interrupt, X86CPU),
|
|
VMSTATE_UINT8(env.nmi_injected, X86CPU),
|
|
VMSTATE_UINT8(env.nmi_pending, X86CPU),
|
|
VMSTATE_UINT8(env.has_error_code, X86CPU),
|
|
VMSTATE_UINT32(env.sipi_vector, X86CPU),
|
|
/* MCE */
|
|
VMSTATE_UINT64(env.mcg_cap, X86CPU),
|
|
VMSTATE_UINT64(env.mcg_status, X86CPU),
|
|
VMSTATE_UINT64(env.mcg_ctl, X86CPU),
|
|
VMSTATE_UINT64_ARRAY(env.mce_banks, X86CPU, MCE_BANKS_DEF * 4),
|
|
/* rdtscp */
|
|
VMSTATE_UINT64(env.tsc_aux, X86CPU),
|
|
/* KVM pvclock msr */
|
|
VMSTATE_UINT64(env.system_time_msr, X86CPU),
|
|
VMSTATE_UINT64(env.wall_clock_msr, X86CPU),
|
|
/* XSAVE related fields */
|
|
VMSTATE_UINT64_V(env.xcr0, X86CPU, 12),
|
|
VMSTATE_UINT64_V(env.xstate_bv, X86CPU, 12),
|
|
VMSTATE_YMMH_REGS_VARS(env.xmm_regs, X86CPU, 0, 12),
|
|
VMSTATE_END_OF_LIST()
|
|
/* The above list is not sorted /wrt version numbers, watch out! */
|
|
},
|
|
.subsections = (const VMStateDescription*[]) {
|
|
&vmstate_async_pf_msr,
|
|
&vmstate_pv_eoi_msr,
|
|
&vmstate_steal_time_msr,
|
|
&vmstate_fpop_ip_dp,
|
|
&vmstate_msr_tsc_adjust,
|
|
&vmstate_msr_tscdeadline,
|
|
&vmstate_msr_ia32_misc_enable,
|
|
&vmstate_msr_ia32_feature_control,
|
|
&vmstate_msr_architectural_pmu,
|
|
&vmstate_mpx,
|
|
&vmstate_msr_hypercall_hypercall,
|
|
&vmstate_msr_hyperv_vapic,
|
|
&vmstate_msr_hyperv_time,
|
|
&vmstate_msr_hyperv_crash,
|
|
&vmstate_msr_hyperv_runtime,
|
|
&vmstate_msr_hyperv_synic,
|
|
&vmstate_msr_hyperv_stimer,
|
|
&vmstate_avx512,
|
|
&vmstate_xss,
|
|
&vmstate_tsc_khz,
|
|
#ifdef TARGET_X86_64
|
|
&vmstate_pkru,
|
|
#endif
|
|
&vmstate_mcg_ext_ctl,
|
|
NULL
|
|
}
|
|
};
|