qemu/target/riscv/insn_trans
Bastian Koppelmann f2ab172867 target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
manual decoding in gen_arith() is not necessary with decodetree. For now
the function is called trans_arith as the original gen_arith still
exists. The former will be renamed to gen_arith as soon as the old
gen_arith can be removed.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-03-13 10:40:50 +01:00
..
trans_privileged.inc.c target/riscv: Convert RV priv insns to decodetree 2019-03-13 10:34:06 +01:00
trans_rva.inc.c target/riscv: Convert RV64A insns to decodetree 2019-03-13 10:34:06 +01:00
trans_rvc.inc.c target/riscv: Convert quadrant 2 of RVXC insns to decodetree 2019-03-13 10:40:46 +01:00
trans_rvd.inc.c target/riscv: Convert RV64D insns to decodetree 2019-03-13 10:34:06 +01:00
trans_rvf.inc.c target/riscv: Convert RV64F insns to decodetree 2019-03-13 10:34:06 +01:00
trans_rvi.inc.c target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists 2019-03-13 10:40:50 +01:00
trans_rvm.inc.c target/riscv: Convert RVXM insns to decodetree 2019-03-13 10:34:06 +01:00