qemu/target/riscv/insn_trans
Anup Patel f008a2d218 target/riscv: Ensure opcode is saved for all relevant instructions
We should call decode_save_opc() for all relevant instructions which
can potentially generate a virtual instruction fault or a guest page
fault because generating transformed instruction upon guest page fault
expects opcode to be available. Without this, hypervisor will see
transformed instruction as zero in htinst CSR for guest MMIO emulation
which makes MMIO emulation in hypervisor slow and also breaks nested
virtualization.

Fixes: a9814e3e08 ("target/riscv: Minimize the calls to decode_save_opc")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230120125950.2246378-5-apatel@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-02-07 08:19:23 +10:00
..
trans_privileged.c.inc target/riscv: Add itrigger support when icount is not enabled 2023-01-06 10:42:55 +10:00
trans_rva.c.inc target/riscv: Ensure opcode is saved for all relevant instructions 2023-02-07 08:19:23 +10:00
trans_rvb.c.inc target/riscv: rvk: add support for zbkx extension 2022-04-29 10:47:45 +10:00
trans_rvd.c.inc target/riscv: Ensure opcode is saved for all relevant instructions 2023-02-07 08:19:23 +10:00
trans_rvf.c.inc target/riscv: Ensure opcode is saved for all relevant instructions 2023-02-07 08:19:23 +10:00
trans_rvh.c.inc target/riscv: Ensure opcode is saved for all relevant instructions 2023-02-07 08:19:23 +10:00
trans_rvi.c.inc target/riscv: Ensure opcode is saved for all relevant instructions 2023-02-07 08:19:23 +10:00
trans_rvk.c.inc target/riscv: rvk: add support for zksed/zksh extension 2022-04-29 10:47:45 +10:00
trans_rvm.c.inc target/riscv: add support for zmmul extension v0.1 2022-06-10 09:31:42 +10:00
trans_rvv.c.inc target/riscv: Introduce helper_set_rounding_mode_chkfrm 2023-01-20 10:14:14 +10:00
trans_rvzawrs.c.inc RISC-V: Add Zawrs ISA extension support 2023-01-06 10:42:55 +10:00
trans_rvzfh.c.inc target/riscv: Ensure opcode is saved for all relevant instructions 2023-02-07 08:19:23 +10:00
trans_svinval.c.inc target/riscv: Ensure opcode is saved for all relevant instructions 2023-02-07 08:19:23 +10:00
trans_xventanacondops.c.inc target/riscv: Add XVentanaCondOps custom extension 2022-02-16 12:24:18 +10:00